Topics covered:

• Hierarchical modelling
• Port connections
• Statement, expression
• Verilog code: Styles of execution
  • Sequential
  • Concurrent
• What Verilog code consists of?
• Different abstraction levels
  • Data flow
  • Behavioural
  • Gate level
• Always
• Fork join, Procedural statements
• Synthesis

1. Implement below MEM_CTRL module using sub module as per the connections shown
   1. Implement using both
      1. Connection by position
      1. Connection by name
   1. No need to run simulation, since we don’t have RTL code implemented for sub modules.
   1. Concept to learn is
      1. How to declare wire for unnamed ports
         1. There wire help connect one module to another module.
      1. Instantiations should be named as u1, u2 so on
         1. If gates are used use: g1, g2
         1. Nets should be named as : n1, n2
   1. Why connection by name is preferred, what are the benefits?
   1. What is default connection?

• Full adder using Half adder
• Parameterizable full adder
• Port connections
  • Module can have 3 possible port directions
    • Input
    • Output
    • Inout
  • When to declare them as reg and net?
    • Any statement inside always or initial block is called as procedural statement
    • All the variables in the LHS of procedural statement must be declared as reg.
    • Any variable that is not a reg, is compulsory net(wire, wand, wor, tri)
      • 95% of cases it is wire
  • Why gate level implementation of full adder does not require any reg declaration?
  • Why data flow implementation of full adder does not require any reg declaration?
  • In below code identify which are reg and wire.
    • //INOUT ports can be on LHS inside always block,
    • assign sda = (master_driving_sda_f == 1) ? sda_t : 1’bz;
    • //2nd process: implementing SPI protocol
    • always @(posedge scl_ref) begin
    • if (prst == 0) begin
    •                 case (state)
    •                                 S_IDLE : begin
    •                                                 master_driving_sda_f = 1;
    •                                                 scl_gated_f = 1;
    •                                                 if (ctrl_reg[0] == 1) begin
    •                                                                 ctrl_reg[0] = 0;
    •                                                                 //Set all transaction parameters
    •                                                                 cur_tx_idx = ctrl_reg[6:4];
    •                                                                 total_txs_to_do = ctrl_reg[3:1] + 1;
    •                                                                 addr_to_drive = addr_regA[cur_tx_idx];
    •                                                                 data_to_drive = data_regA[cur_tx_idx];
    •                                                                 count = 0;
    •                                                                 //next state
    •                                                                 next_state = S_START;
    •                                                 end
    •                                 end
    •                                 S_START : begin
    •                                                 master_driving_sda_f = 1;
    •                                                 scl_gated_f = 1;
    •                                                 sda_t = 0;
    •                                                 #(START_DELAY);
    •                                                 scl = 0;
    •                                                 next_state = S_ADDR;
    •                                 end
    •                                 S_ADDR : begin
    •                                                 master_driving_sda_f = 1;
    •                                                 scl_gated_f = 0;  //Clock is running now
    •                                                 sda_t = addr_to_drive[count];
    •                                                 count = count + 1;
    •                                                 if (count == 8) begin //for 8 clocks we continue to stay in S_ADDR state only
    •                                                                 next_state = S_ADDR_ACK;
    •                                                                 count = 0;
    •                                                 end
    •                                 end
    •                                 S_ADDR_ACK : begin
    •                                                 master_driving_sda_f = 0;  //slave will be drivign SDA pin at this point, master will be in sampling mode
    •                                                 scl_gated_f = 0;  //Clock is running now
    •                                                 if (sda == 0) begin
    •                                                                 $display(“Slave has acknowledged the address phase”);
    •                                                 end
    •                                                 if (sda == 1) begin
    •                                                                 $display(“ERROR : Slave has not acknowledged the address phase”);
    •                                                 end
    •                                                 next_state = S_IDLE_BW_ADDR_DATA;
    •                                 end
    •                                 S_IDLE_BW_ADDR_DATA : begin
    •                                                 master_driving_sda_f = 1;
    •                                                 scl_gated_f = 1;  //Clock is running now
    •                                                 count = count + 1;
    •                                                 if (count == 4) begin //for 8 clocks we continue to stay in S_ADDR state only
    •                                                                 next_state = S_DATA;
    •                                                                 count = 0;
    •                                                 end
    •                                 End
    • End
• Fork join
  • What time below display will happen?
  • Sequential execution
    •  Statements run one after other.
    •  Ex:  task run();

                #5 $display(“ENTRY 1”);  //what time print will happen?

                  #2 $display(“ENTRY 2”);   //

                  #5 $display(“ENTRY 3”);   //

  endtask

•  Concurrent execution
  •  Statements run concurrently.

        task run();

                fork  //all the statement inside will run concurrently

                #5 $display(“ENTRY 1”);   //

                  #2 $display(“ENTRY 2”);   //

                  #5 $display(“ENTRY 3”);   //

                join

endtask

• Continuous assignment
  • Write two example codes of any continuous assignments.
  • Write two example codes of any procedural statements.
• What is wrong with below code?
  • initial begin
  •  assign a = b+c; //Wrong: continuous assignments can’t be written inside initial
  •  end
• What is wrong with below code?
  • initial begin
    • initial begin
      • a = 10;
    • end
  •  end
• What is wrong with below code?
  • initial begin
    • always @(b) begin
      • a = b;
    • end
  •  end
• What is wrong with below code?
  • initial begin
    • task add();
    • endtask
  •  end
  • However calling add inside initial is allowed
• What is wrong with below code?
  • initial begin
    • and g1(a, b, c);
  •  end
• Write a simple continuous assignment-based example to prove that order in which we write continuous assignment statements does not impact the output of the design.
• Implement 4×1 Mux using gate level.
  • Truth table, Kmaps, Boolean expression
• List down various procedural blocks in Verilog
• What time below initial statements will complete.
  • module sample;
  • initial  begin//this will start at 0 simulation time
  •                 $display(“%t : ENTRY-1”, $time);     //
  • end
  • initial begin  //this will start at 0 simulation time, end at 60 units.
  •                 #50;
  •                 $display(“%t: ENTRY-2”, $time); //Executes at 50 time
  •        #10;
  • end
  • initial begin
  • fork
  •                 #5 $display(“ENTRY 1”);   //5
  •                   #2 $display(“ENTRY 2”);   //2
  •                   #5 $display(“ENTRY 3”);   //5
  • join
  • end
  • endmodule
• Synthesis examples : what circuit below codes will infer and draw the circuit.
  • Q1
    • always @(posedge clk) begin  //this will infer sequential logic => Flip flops
    •  {co, s} = a + b + cin;
    •  end
  • Q2
    • always @(a or b or cin) begin
    •  {co, s} = a + b + cin; 
    •  End
  • Q3 : How many FF does below circuit synthesize to?
    • always @(posedge clk) begin
    • a = b+c;  //a : 4 bit vector, b, c : 6 bit vector
    • end
    • Is above logic combinational or sequential?
      • How many FFs?
• What is the significance of below sensitivity list.
  • Q1
    • always @(signal1 or signal2) begin
    •                                 ..
    • end
  • Q2
    • always @(posedge signal1 or posedge signal2) begin
    •                                 ..
    • end
  • What does Q1 would infer, Q2 would infer?
    • Combinational or sequential?
• Below code what all times, ENTRY-1 and ENTRY-2 displays will happen?
  • module tb;
  • reg clk;
  • initial begin
  •                 clk = 0;
  •                 forever #5 clk = ~clk; //TP=10 tu
  • end
  • always @(posedge clk) begin
  •                 $display(“%t: ENTRY :: 1”, $time); 
  • end
  • //multi cycle path: Path which takes more than one clock cycle.
  • //If we are already inside the always block, we will not enter again even if sensitivity list changes
  • always @(posedge clk) begin //#5, #15(don’t enter), #25(enter), #35(don’t enter), #45(enter)
  •                 #15;
  •                 $display(“%t: ENTRY :: 2”, $time); 
  • end
  • initial begin
  •                 #100;
  •                 $finish;
  • end
  • endmodule
• What is multi cycle path?
  • Provide an always block example which results in multi cycle path.
• Explain below statements with an example.
  • initial is suitable for testbench coding.
  • Always is suitable for design coding.
• Write a logic to generate clock using always block, no forever
  • Clock of #10 TP
• What is issue with below code?
  • What is issue with below code?
  • always begin  //sensitivity list is empty, it will always enter
  • clk = ~clk;
  • end
• Implement half adder using always block
• Write Verilog code for below circuit.
  • Using always and assign, write the Verilog code
    • Assume it is synchronous reset
    • Reset takes effect only at the positive edge of clock

1. How to approach
   1. How many FFs are there?
      1. Do they use same clock?
         1. Yes, single always is sufficient
      1. Is there is reset?
         1. Yes,
         1. At reset, make Y & W as 0
      1. If reset not there
         1. Y will be and of a & b
         1. W will be inverse of c
2. Write Verilog code for below circuit
   1. Res and rst both are same
   1. Both flops have same clk
   1. Hint: any unnamed should be named
3. Write Verilog for below circuit
   1. All FF on same clock and same reset
4. Write Verilog for below circuit
   1. FF1 and FF3 are on same clock (clk1)
   1. FF2 on different clock (clk2)
      1. Though diagram is different.
   1. As you get time, check all behavior by running Verilog simulation.
5. In below code, what time b, c, and d will take the values?
   1. initial begin
   1.                 #5 c = 1;
   1.                 #5 b = 0;
   1.                 #5 d = c;
   1. end
6. How many processes are in below code? at what time c, b, and d assignment will happen?
   1. How many processes are there in below code?
   1. initial begin
   1. fork
   1.                 #5 c = 1;
   1.                 #5 b = 0;
   1.                 #5 d = c;
   1. join
   1. end
7. How many processes are in below code? at what time c, b, and d assignment will happen?
   1. initial begin
   1. fork
   1.                 #5; c = 1; 
   1.                 #5; b = 0;
   1.                 #5; d = c;
   1. join
   1. End
8. How many processes are there in below code? at what time c, b, and d assignment will happen?
   1. initial begin
   1. fork
   1. begin  //since we used begin, end, it becomes one process.
   1.                 #5 c = 1;
   1.                 #5 b = 0;
   1.                 #5 d = c;
   1. end
   1. join
   1. end
9. How many process in below code?
   1. initial begin
   1. fork
   1.                 begin
   1.                 #5 c = 1;
   1.                 #5 b = 0;
   1.                 end
   1.                 #5 d = c;
   1. join
   1. end