Concepts to learn:   


  1. List down AHB IC features?
  2. Come up with AHB IC testplan?
    1. Feature, scenario, testname, test intent, status
  3. Draw AHB UVC architecture
    1. Master
    1. Slave
  4. What is mean by configurable AHB IC?
    1. How do we ensure that AHB IC with configurable number of masters and slaves?
  6. Setup AHB UVC  & AHB Interconnect Template environment
    1. Top(module) -> test_library-> AHB_env -> AHB_agent -> AHB Drive, Sequencer, mon, coverage
      1. Test case component definition
      1. Interface instance
        1. Multiple instances (count = masters + slaves count)
        1. One APB interface
      1. DUT instance(if AHB interconnect is coded as module)
      1. Clk, rst
      1. Add interface to configuration DB
        1. Uvm_config_db#(virtual ahb_intf)::set()
      1. AHB assertion module
      1. Run_test called from initial
    1. Slave Model
      1. Coded as SV model
        1. Used AHB Slave UVC
        1. Instintiate in AHB environment class
        1. This is called slave UVC (AHB_bfm_slave + AHB_monitor)
      1. Coded as a module (using AHB_slave module to model slave behavior)
        1. Instantiate AHB_slave in top module
        1. Connect using ports
  7. Top module
    1. Test case
    1. Rst, clk
    1. Generate clk, rst
    1. AHB_intf instantiation
  8. Code
    1. File which has got all test case definitions
    1. Coded as a base test and functional test
    1. Base test : all the things common to all tests
    1. Functional test:
      1. Extend from base test
      1. Code things are unique to this test
        1. Instantiate a sequence
        1. Create sequence
        1. Sequence.start(sqr)
        1. Change number of master, slaves
        1. Raise objection, drop objection (if start is used to run sequence)
  9. Code
    1. AHB Master and slave agents are instantiated as dynamic array
    1. Instantiate ahb_ic if it is coded as a class
    1. Create all master and slave agents using create
      1. Ensurte that each gets unique name by using $sformat
      1. Assign master_no and master_slave_f for each of the cmponents below every agent
  10. Code
    1. Coded to support both master and slave agent behavior
      1. Master_slave_f used to decide behavior
    1. Master : all 4 components(driver, sqr, monitor, coverage) will be there
    1. Slave: only 2 components(driver, monitor) will be there
  11. Code
    1. Coded to support both master and slave driver behavior
      1. Master_slave_f used to decide behavior
    1. Code Build_phase to get the interface handle specific to current master
      1. Use master_no to get exact interface
    1. Master driver
      1. Get items from seq_item_port
      1. Drive them on AHB interface by calling drive_tx method
        1. Arbitration phase
        1. Request & data phase happening concurrently, except 1st address phase and last data phase
      1. Once drive completes, call seq_item_port.item_done
    1. Slave driver
      1. At every positive edge check for valid request(Htrans is NONSEQ or SEQ) from master
      1. When SEQ or NONSEQ request happens, store the address and control signals to temporary variables
        1. All this implemented using case(vif.htrans)
        1. Combination of current HTrans and Prev Htrans(lost clock) will tell how to handle current data phase(should it be ignored or considered?)
        1. All slave need to decide is
          1. Whether to capture current address phase(decided using current Htrans)
          1. Whether to capture data phase (decided using previous htrans)
      1. Code
        1. Monitor interface at every positive edge, look for valid transtion
      1. Code
  12. Code
  13. Code
  14. Code
  15. Code
    1. Write tests targeting multiple master and slave’s
    1. Whenever we change master count, slave count, ensure that interface ahndles are created as per need

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