DUT instance(if AHB
interconnect is coded as module)
Clk, rst
Add interface to configuration
DB
Uvm_config_db#(virtual ahb_intf)::set()
AHB assertion module
Run_test called from initial
Slave Model
Coded as SV model
Used AHB Slave UVC
Instintiate in AHB environment
class
This is called slave UVC
(AHB_bfm_slave + AHB_monitor)
Coded as a module (using
AHB_slave module to model slave behavior)
Instantiate AHB_slave in top
module
Connect using ports
Top module
Test case
Rst, clk
Generate clk, rst
AHB_intf instantiation
Code test_lib.sv
File which has got all test
case definitions
Coded as a base test and
functional test
Base test : all the things
common to all tests
Functional test:
Extend from base test
Code things are unique to this
test
Instantiate a sequence
Create sequence
Sequence.start(sqr)
Change number of master, slaves
Raise objection, drop objection
(if start is used to run sequence)
Code ahb_env.sv
AHB Master and slave agents are
instantiated as dynamic array
Instantiate ahb_ic if it is
coded as a class
Create all master and slave
agents using create
Ensurte that each gets unique
name by using $sformat
Assign master_no and
master_slave_f for each of the cmponents below every agent
Code ahb_agent.sv
Coded to support both master
and slave agent behavior
Master_slave_f used to decide
behavior
Master : all 4
components(driver, sqr, monitor, coverage) will be there
Slave: only 2
components(driver, monitor) will be there
Code ahb_driver.sv
Coded to support both master
and slave driver behavior
Master_slave_f used to decide
behavior
Code Build_phase to get the
interface handle specific to current master
Use master_no to get exact
interface
Master driver
Get items from seq_item_port
Drive them on AHB interface by
calling drive_tx method
Arbitration phase
Request & data phase
happening concurrently, except 1st address phase and last data phase
Once drive completes, call
seq_item_port.item_done
Slave driver
At every positive edge check
for valid request(Htrans is NONSEQ or SEQ) from master
When SEQ or NONSEQ request
happens, store the address and control signals to temporary variables
All this implemented using case(vif.htrans)
Combination of current HTrans
and Prev Htrans(lost clock) will
tell how to handle current data phase(should it be ignored or considered?)
All slave need to decide is
Whether to capture current
address phase(decided using current Htrans)
Whether to capture data phase
(decided using previous htrans)
Code ahb_monitor.sv
Monitor interface at every
positive edge, look for valid transtion
Code ahb_coverage.sv
Code ahb_sequence_library.sv
Code ahb_ic.sv
Code ahb_scoreboard.sv
Code test_lib.sv
Write tests targeting multiple
master and slave’s
Whenever we change master
count, slave count, ensure that interface ahndles are created as per need
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