Concepts to learn:   


  1. What is AHB Interconnect?
  2. Where do we use AHB interconnect?
    1. Any design which requires connecting multiple AHB based masters to multiple AHB based slaves
      1. Master: Processor, GPU processor
      1. Slave: KBD controller, Memory, Timing controller
  3. How many maximum master and slaves does AHB support?
    1. 16 masters
    1. 16 slaves
  4. AHB features?
    1. Burst transfers
    1. Split & retry transfers
    1. Single clock cycle handover
    1. Aligned transfers
    1. Non-tristate implementation
  5. How many interface does AHB interconnect has?
    1. 1 APB interface for configuration
    1. Multiple AHB interfaces : masters
    1. Multiple AHB interfaces: Slaves
  6. Draw AHB architecture diagram with 3 master, 4 slaves and 1 interconnect?
  7. Draw AHB interconnect internal architecture diagram
  8. Does AHB IC has configuration registers?
    1. Yes, these rgisters are used for slave address range configuration
    1. S0_START, S0_END, etc
  9. How AHB interconnect works?
    1. 1st step: Design configuration
      1. Program design for all slaves start and end addresses
    1. 2nd step: Master’s will generate write, read transactions targeting slaves
      1. AHB Interconnect does arbitration to give grant to a specific master
        1. Priority basis and slave readyness
      1. Interconnect will route these txs to various slaves using address decoding
  10. Explain round robin arbitration in AHB interconnect?
    1. req [31:0] type_of_arbitration;
  11. Explain priority based arbitration in AHB interconnect?
  12. How does Split transaction work in AHB? Explain using AHB interconnect diagram?
  13. How Retry transactions work in AHB? Explain using AHB interconnect diagram?
  14. How Retry response is different from Split response?
  15. What is early burst termination?
    1. Process of termination a ongoing burst transfer
    1. EBT is initiated by a slave or interconnect
      1. Slave by issuing Split or Retry
      1. Interconnect when a higher priority master makes request, given that current ongoing transfer is non-locked
  16. Explain significance of each signal in AHB protocol?
    1. Hbusreq
    1. Hgrant
    1. HLock
    1. Hmaster
    1. HSPlit
    1. HAddr
    1. HSize
    1. HBurst
    1. HProt
    1. HTrans
    1. Hwdata, HRdata
    1. Hready
  17. Explain 2 cycle response in AHB?
    1. Used by the slave for SPLIT, RETRY and ERROR responses
    1. It is used to ensure that next address phase is not driven by the master
  18. How handshaking works in AHB?
    1. What signals are involved?
    1. Explain using a timing diagram
  19. Draw the timing diagram for following requirements
    1. HADDR = 32’h1000_0008
    1. HSize=2, HWrite=1
    1. HBurst = WRAP4
  20. For above, list down memory location where writes will happen?
  21. How does wrap transfer work?
  22. What is need for INCR burst type?
  23. What is maximum data bus size supported by AHB?
  24. What is the significance of 1KB boundary?
  25. How master introduces wait states? How slave introduces
  26. Given a transfer with different burst, use address value as criterial to know exact locations where data is written?
  27. If slave has issued Split response, how does it indicate its readiness to specific master?
    1. HSPLIT[15:0] => HSPLIT[5] = 1 => slave is ready to respond to master[5]

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