USB3.2 protocol training

mention of USB, PCIe, DDR in resume opens up quite of few job opportunities..that is the importance of these protocols in current SoCs..

All high speed protocols like USB3, PCIe, SATA, UFS, etc are all based on OSI architecture. Course focus on teaching all the required concepts of different layers in USB. Course also cover design & testbench implmentation for Protocol, link and physical layers of USB.

  • Week#1 & 2
    • USB2.0 protocol in depth
    • USB3.0/3.1/3.2 protocol overview
    • USB3.2 System description
    • Enhanced super speed bus  Architecture
      • Physical Layer
      • Link layer
      • Protocol layer
  • Week#2
    • Enhanced super speed data flow model
    • Pipes
    • Enhanced super speed protocol overview
    • Data bursting
    • IN, OUT Transfers
    • Control, Bulk and Isochronous transfers
    • Device notifications
  • Week#3
    • Protocol Layer
    • Enhanced Superspeed transactions
    • Packet types
    • Link management packet
    • Transaction packet
    • Data packet
    • Isochronous Timestamp packet
    • Addressing Triple
    • Route String field
  • Week#4
    • Link Layer
    • Byte ordering
    • Link management and flow control
    • Link error rules and recovery
    • PowerOn Reset and Inband Reset
    • Link Training and Status State Machine
  • Week#5
    • Physical Layer
    • Symbol encoding
    • Link initialization and training
    • Clock and jitter
    • Signaling
    • Transmitter specifications
    • Receiver specifications
    • Low frequency periodic signaling
    • Receiver detection
    • 2 Device Framework
  • Week#6
    • Power Management
    • Device framework
    • USB device requests
    • Standard device requests
    • USB protocol analyzer concepts
Course USB2.0 and USB3.0/3.1/3.2 Protocol Training
Duration 6 weeks
Next Batch

Adhoc

Currently there is no live sessions planned. You may enrol for e-learning course for self paced learning, with option to join upcoming batch with no additional cost. Trainer will be accessible for doubt clarifications.

Mode of Training Course offered as recorded Videos for self paced learning

What are the Course Prerequisites?

  • Exposure to standard bus protocols
  • Exposure to Testbench component coding using SystemVerilog

What if I miss few sessions during course?

    • Each session of course is recorded, missed session videos will be shared

Course has started few weeks back, can I still join the course in between?

  • Yes, You will have option to view the recorded videos of course for the sessions missed
  • You will have option to repeat the course any time in next 1 year

Do you offer support after course completion?

  • Yes, Course fee also includes support for doubt clarification sessions even after course completion
  • You have option to mail you queries
  • Option to meet in person to clarify doubts

USB2, USB3, and USB4 specification
USB quick reference manual
Session notes
Course assignments

Trainer Profile

  • 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
  • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
  • Experience of working on multiple complex module level projects
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