UTMI will be present at both Host side & Core side


XcvrSelect = 0 => HS transmitter & receiver enabled
XcvrSelect = 1 => FS transmitter & receiver enabled

TermSelect = 0 => HS, 1 => FS

D+ , D-
0 0 => SE0
0 1 => K
1 0 => J
1 1 => SE1

Device is sending Chirp K => Device is driving 0 on D+, 1 on D-, spec also for how much time?

UTMI Driver & Sequencer will replace the host behavior, UTMI driver will be
actually sending ChirpK & J in response to USB core Device Chirp K

SPeed negotiation:
Power on -> FS mode -> device attached -> Normal -> Suspend -> Reset -> Speed negotiation seqeunce -> Normal data transfers

Data transfers:
Transmit: Device giving data to UTMI host
signals: TxValid(device to host) & TxReady (host to device ack)

Control Transfers:

Isochrnous transfers:

Interrupt transfer

AHB (Function) interface: (Master interface)

UTMI interface: (Master interface)

SRAM interface: (slave interface)

TB coding:


WB Protocol:
wb_addr_i : where we want to do write or read
wb_data_i : data to be written(wb_we_i = 1)
wb_sel_i : which all bytes of data_i are valid(1 bit for each of 8 bit of data_i bus)
wb_data_o : data read
wb_we_i : Write or read
wb_cyc_i : continutaiton of previous transfer
wb_stb_i : current transfer on bus is valid
wb_ack_o : slave is ready to accept the transfer

At any +edge of clock, if wb_cyc_i, wb_stb_i, wb_ack_o are high, at the point addr is valid, data is valid

CLock edge 1 => WB master will drive wb_addr, wb_cyc = 1, wb_stb=1, wb_data_i is also driven
CLock edge 2 => wb slave will acknogliedge its readyness by driving wb_ack_o = 1=> at this edge transfer is complete, master can initiated new transfer clock edge 3(not on 2)

Defining WB_tx?


USB funcitonality:

  1. register configruation : WB
  2. Enumeration : UTMI
  3. speed negotiation : UTMI
  4. data transfers : UTMI
  5. dma wr/rd’s : WB
  6. interrupt handling : WB
  7. suspend/resume : UTMI

User needs to develop seqeunces specific to above functionality
register_config_seq, dma_wr_rd_seq, int_handling_seq (WB_SEQ_LIBRARY)
Enumeration_seq, speed_neg_seq, data_transfer_seq, susp_res_seq (UTMI_SEQ_LIBRARY)

  1. Configuration keeps changing from test to test


  1. To program a register we discussed 2 ways of doing
    1st: without using register model
    `uvm_do_with(req, {req.addr == register_address; == data_to_write;})

2nd: using register model
reg_block_name.register_name.write(status, data_to_write);

  1. Every test case goes in following steps(applicable to every design)

o generating frames

  1. Powering up verificaiton

6.100/7 = 2
data_in = 100
poly = 7
crc5 = 2


in Pkt, we talk interms of bit arrays

  1. //16 EPs
    //EP0 : control
    //EP1-5 : bulk
    //EP6-10 : ISO
    //EP11-15 : interrupt


Before I start test(pkt geenration), I need to decide which ep supports which
tfr type? I should constraint token_pkt.endp value accordingly

  1. ENd goal : create a usb bulk test

speed neg
data transfer


  1. UTMI Monitor can send informaiton to refernece model in different ways
  1. Pkt level communication between utmi monitor & refrence model
    o token, sof, data, hs, special
    o Analysis port only supports one type of pkt only
    o uvm_analysis_port#(sof_pkt) ap; //ap only supports sof pkt, it will not support data pkt, hs pkt, token pkt, etc
    o solutionL: declare AP with base_pkt as communication data
    o uvm_analysis_port#(base_pkt) ap; //all pkts are derived from base_pkt, by virtue of polymorphism we will be able to send any pkt derived from base_pkt
  2. Functional coverage for USB2.0 core
  1. Reference model implementation
    o DUT mimicked model
    o if SOF comes in to USB core?
    o DUT will check if pid is proper(pid[7:4] == ~pid[3:0]) (if it fails?? int_src_reg::pid_error it will be asserted in int_src rgister)
    o is frame_no in series? (saves previous frame_no, compares it with current frame_no)
    o is crc5 correct? (fails , crc_error in int_src)
    o What refreence model should do with SOF pkt?
    o same 3 steps as above
    o Reference model instead of updating DUT reister, it will udpate register model’s register o After SOF, TOKEN pkt will come
    o what DUT does?
    o pid check?
    o crc5 check
    o addr comparision with my FA? match means process the next data pkt and hs pkt, else drop them since this Token pkt is for some otehr device
    o ep_no, check if the ep_no is configured in DUT, get all the ep information, process the next incoming or outgong data pkt accordingly o What refreence model should do with TOKEN pkt?
    o same as what DUT does o DATA PKT handling?
    o DUT will check pid, crc16
    o if OUT pkt, data will be written to sram model, generate dma_req to funciton controller
    o if IN pkt, dma_req generaetd to FC, start reading data from sram model, send the IN pkt to UTMI interface o REFENCENCE model will not do exactly the way DUT is doing above
    o pid, crc16 check
    o it will not write data to sram, it will make sram tx out of this data, it will compare these tx with txs happening on sram interface/utmi itnerface
    o it will not also generate dma_req
    o it will not write/read to/from sram

o WHile doing all above operations, DUT will access registers to decide how to handle pkts at different stages
o ex: pid error happned, should I generate int or not? int_msk.pid_error_enable
o DUT got token & data pkt, should I send HS pkt? check ep_no, type of ep, if ep_type is ISO, then don;t send, else send

 o Reference model also will refer to register model at each stage to decide on how to handle each pkt
  1. Reference model implementation
    o base class: uvm_scoreboard
    o it will have 3 analysis implmentation ports to get data from wb_mon, sram_mon, utmi_mon each
    o it should analuze the pkts the way DUT does
    o data comparision


  1. Many to one connection
  1. Env
    utmi_agent.mon.ap.connect(ref_model.imp_utmi); //ap.write happens automatically ref_model.write_utmi gets called

while (1) begin
pktQ.pop_front(pkt); //this will be 0 delay loop

while (1) begin
mbox_pkt.get(pkt); //this will be blocking

  1. WB TX conversion to SRAM Format

WB_TX : 100
SRAM_TX : 100/4

WB_TX : addr => addr >> 2;
data => same
wr_rd => same

  1. COnverting UTMI PKTS in to SRAM format

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