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­­­­Specman e Training with Hands on project

Specman e training overview:

  • ‘e’ language is a HVL, proprietary of Cadence. It is more powerful & user friendly than Systemverilog. It is based on Aspect oriented programming(AOP). Most the important features unique to UVM with respect to other methodology all are taken for eRM(original form of UVM). Fact that SV is promoted by IEEE and it is promoted as HDVL, made SV win over ‘e’. Learning Specman e, brings in lot more value addition to the engineer.
  • Specman e training will focus on all ‘e’ language constructs including AOP, Units, Structs, Data types, loops, coverage, etc. Training will also focus on eRM methodology. Training will involve a hands on project with complete exposure from specification to verification closure.

Schedule & Fee:

  • 8 weeks training
  • 8 hours per week (2 sessions on Saturday & Sunday, 4 Hours each)
  • Fee: 15,000
  • Next Batch: Adhoc (majority of requirements are on SV training, e training is provided on need basis)

Agenda:

  • e language constructs   (5 weeks)
  • Hands on verification project using eRM  (3 weeks)

Pre-requisites:

  • Object Oriented Programming
  • Intermediate exposure to test bench development using Verilog & SV

 

Trainer Profile

  • 12+ year’s exp. in functional verification with exposure to multiple SOC, Subsystem and module level verification projects.

 

Course Content

  • Week#1,2
    • E language constructs
      • Basics
        • Basic e Syntax
        • Types and Numbers
        • Importing e files
      • Data types
      • Units, Structs, Fields, and Subtypes
      • Ports
      • Generation Constraints
      • Events
      • Time-Consuming Actions
    • Week#3,4
      • Coverage Constraints
      • Macros
      • Checks and Error Handling
      • Methods
      • Packing and Unpacking
      • Stimulus creation
      • Stimulus variation
      • Driving inputs
      • Abstraction conversion
      • Pre-run and on-the-fly generation
    • Week#5
      • Checking results
      • Modeling Input-Output channels in e
      • Coverage
      • Control Flow Actions
      • List Pseudo Methods Library
      • Preprocessor Directives
      • Predefined Methods Library
      • Predefined Routines Library
      • eRM methodology, Coding Guidelines
    • Week#6-8
      • Industry standard project(design verification using Specman E)
      • Testbench architecture, testcase coding, sequence coding, coverage analysis

 

Trainee Assessment:

  • Test to assess student learning at the end of course

 

Course Material

  • Individual session notes
  • e Language reference manual
  • e Lab files, including example solutions that illustrate proper and efficient coding styles