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Trainer Profile

  • Multiple trainers, each with rich experience of SOC subdomain. All working in top-3 product companies.

FAQ:  

  • Course pre-requisites?
    • Working knowledge of SV, capable of setting up testbench for simple designs
  • What if few sessions missed?
    • We will cover up missed sessions
  • Course has started few weeks back, can I still join the course in between?
    • Missed sessions will be covered up, option to repeat the course in next 1 year*

Course Content:

  1. SOC design & verification flow overview
  2. SOC Design concepts
  3. Processor boot concepts
  4. SOC Verification : Important aspects
  5. Testbench
  6. Setting up SOC TB environment
  7. SOC Subsystem overview (Processor, High speed, Low speed, Modem, Multimedia subsystem)
  8. Testplan
  9. Testcase Flow
  10. Testcase Coding (C & SV)
  11. Running testcases & regression
  12. SOC Test debug
  13. Typical testcase issues
  14. Verification closure
  15. Performance requirements
  16. Gate level simulations
  17. Power Aware Simulations
    1. PAGLS
  18. EVCD generation
  19. Vector runs on VT setup
  20. Generating binaries for running on tester
  21. ECO
  22. RMA
  23. UVC in Testbench setup & sequence usage in SV testcase

 

 

  1. SOC FLOW:
  • SoC Architecture
  • Design Integration
    • Spy glass,
  • Functional Verification
  • Formal Verification (Connectivity Checks)
  • PA RTL simulations
  • GLS
  • PA GLS simulations (UPF)
  • Vector evcd generation
  • VT simulations on testers
  • Post silicon validation (VI)

 

  1. Design:
  • SoC Architecture
  • SoC Interconnects & NOCs
  • NoC Overview – Types of NOCs, purpose and diagram
  • SoC Digital & Analog Components
  • SoC Address Mapping
  • SoC Interrupt Mapping
  • SoC Frequency Plan
  • SoC Performance requirements
  • Features
  • DPLL
  • SoC Memories: Msg ram, Iram, DDR, Flash
  • SoC Subsystems
  • Low Power Verification
    • UPF

 

  1. Important aspects:
  • SoC Architecture, understanding transaction matrix
  • Processor boot, SCF file,
  • interconnects
  • Memory preloading
  • DDR initialization
  • PLL locking(LMN values)
  • TIC interface
  • Clock domains
  • Different clock mode
  • XO mode, at-speed mode
  • Interrupt handler
  • Processor interfaces: interfaces meant for fetching instruction, data code
  • I/O’s of SOC: Dedicated IO’s, and GPIOs
  • GPIO purpose : Pad muxing
  • CDC
  • Cycle slips
  • MMU, Physical address, virtual address
  • ARM instruction set basics
  • Types of verification : how they are different
  • Processor architectures
    • ARM, ARC, DSP
    • Cortex A series, M series
    • Impact on design architecture
  • Basics of ARM processors
    • Types of processors – Cortex-M series, A series.
    • ARM C, ASM compiler, linker.
    • Caches (L1 and L2).
    • Generic Interrupt controller.
    • Exceptions, Events – Types of Exceptions (Edge, Level), Source of Exceptions, How to handle.
    • Debug system – Basics of ARM debug sub system.
    • Scatter files.
    • How to set reset location to start booting.
    • Loading C code into memories – Front door, back door.
    • ARM Instruction example

 

 

  1. SOC Testbench Setup
  • SoC environment structure
  • SoC TB Architecture
  • Integrating UVC in to SoC TB
  • SoC Processor-TB interaction

 

  1. Testplan:
  • register wr-rd, reset tests
  • Interrupt tests
  • targeting different frequency plans
  • Feature(use-case) tests
  • power aware tests
  • Fuse tests
  • End to end data transfer tests
  • Booting from different testcases
  • Address decoding access tests
  • Connectivity tests

 

  1. Testcase Flow:
  • TIC mode
  • Functional mode
  • Device Initialization
  • DDR initialization
  • Enabling DDR access to different processors
  • Processor boot sequence
  • Processor boot from different memories
  • C test Main function
    • Power uncollapse
    • Functional test

 

 

  1. Coding testcases:
  • Listing down test requirements, pass criteria
  • Power domains to be up
  • clock domains to be up, required frequencies
  • Understanding required flow to implement testcase
  • knowing library functions to implement above flow
  • understanding handshake between Native & SV code

 

  1. Setting up environment:
  • Design baseline
    • all design sub component latest baselines
  • verif baseline
    • all verif sub component latest baselines
  • Updating env for custom baseline

 

 

  1. Running testcases & regression:
  • Command line
  • sim_gui mode
  • Command line options
  • using force files, timing corners, frequency plans

 

  1. Debugging tests:
  • tarmac log
  • List file
  • mpf file
  • log
  • Wave dump debug
  • Message based debug
  • Warnings, errors

 

  1. Typical testcase issues:
  • Processor not booting
  • register looping
  • Not working at current frequency plan
  • pll not locked
  • Memory not preloaded
  • clocks not running
  • Access is not enabled to register or memory space
  • Simulation not proceeding in time
  • Simulation is proceeding in time but not completing (looping)
  • Interrupt not serviced
  • interrupt not generated
  • Signal not sampled
  • sub module functional issues
  • Denali errors
  • Memory loading ‘x’ debug
  • tied signals, unconnected ports

 

  1. Understanding chip stages:
  • RTL code freeze
  • Base tapeout
  • Metal tapeout
  • ECO update
  • CS (customer shipment)
  • RMA

 

  1. Verification closure:
  • Regression 100% pass
  • 100% toggle coverage
  • reviews high level & low level
  • Performance requirements
  • Power reqs met

 

  1. Performance requirements?

 

  1. Gate level simulations:
  • Significance
  • choosing tests for GLS

 

  1. EVCD generation:
  • Format?
  • Why?
  • choosing tests for GLS

 

  1. Vector runs on VT setup
  • production vectors
  • characterization vectors

 

  1. Generating binaries for running on tester
  • Vector debug

 

  1. ECO:
  • What stage ECO is issued

 

  1. RMA:
  • Significance?

 

  1. Misc:
  • SoC Architecture:
  • SoC Interconnects
  • SoC Digital & Analog Components
  • SoC Address Mapping
  • SoC Interrupt Mapping
  • SoC Frequency Plan
  • SoC Performance requirements
  • Features
  • PLL
  • SoC Memories: Msg ram, Iram, DDR, Flash

 

  1. Processor booting from different memories
  2. UVC in Testbench setup & sequence usage in SV testcase

SoC Design & Verification

  • Morethan 60% of verificaiton work in VLSI is based on SOC & SUbsystem verificaiton. It becomces essential for every verificaiton engineer to gain expertise on SoC & Subsystem verificaiton concepts. The course is targeted towards teaching complete SOC flow, starting from Architecture, usecases, testbench environemtn setup, testcase coding and testcase debug techniques.
    • SoC Design Architecture
    • Usecase listing down
    • Testbench Architecture
    • Testcase coding
    • Testcase debug
    • GLS setup & debug
    • Vector setup & debug
  • Course SoC Design & Verification
    Duration 7 weeks
    Next Batch 9-December
    Demo Session 9-December (10:30AM - 01:30AM)
    Registration 10-December (after attending demo session on 9-December)
    Schedule Both Saturday & Sunday(10:30AM - 01:30AM India time)
    Course repeats every 10 weeks
    Fee INR 10000/- + Tax
    Tool Questasim
    Mode of training Classroom training at VLSIGuru Institute(Horamavu)
    Online training using live training sessions
    Tool Access 24X7 access using VPN
    Certificate Issued based on 50% assignment completion as criteria
    Batch Size 20
    Assignments 20
    Trainer 12+ Years exp in RTL design & Functional verification
    • What are the Course Prerequisites?

      • Expertise on SystemVerilog Language
      • Exposure to Testbench component coding using SystemVerilog
    • Does course cover practical sessions on UVM usage?

      • Each aspect of course is supported by lot of practical examples
      • AHB Interconnect is reference design from Session#1 towards implementing and learning different UVM aspects
      • All UVM course examples, AHB UVC, AHB Interconnect and USB2.0 Core Verification environment implemented from scratch as part of sessions
      • Dedicated full day lab sessions to ensure student does complete testbench development from scratch
    • Is it possible to cover so many things in 9 weeks?

      • We have done it for 23 Batches so far, next batch is no exception
      • Course requires student to spend at least 6+ hours of time a week to revise the concepts
    • What if I miss few sessions during course?

      • Each session of course is recorded, missed session videos will be shared
    • Course has started few weeks back, can I still join the course in between?

      • Yes, You will have option to view the recorded videos of course for the sessions missed
      • You will have option to repeat the course any time in next 1 year
    • Do you offer support after course completion?

      • Yes, Course fee also includes support for doubt clarification sessions even after course completion
      • You have option to mail you queries
      • Option to meet in person to clarify doubts
  • SoC architecture docs, protocol specification docs, etc.
  • Target Audience:
    • Verification engineers who have only exposure to Module level verificaiton, would like to widen verification exposure.
    • MTech & BTech freshers who are well versed with SV, and would like to learn advanced verification
    • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
    • Engineering college faculty looking to enhance their VLSI skill set
  • Trainer Profile
    • 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
    • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
    • Experience of working on multiple complex module level projects
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