Learning Simulation Debug

80% of functional verification cycle is spent on developing testcases and debugging test failures. Hence every engineer needs to have good debug skills. Below I have listed few concepts that are commonly used.

• Debug using display messages in Transcript or Log file
• Debug using ARM tarmac log, and List file
• Debug by tracing design RTL files
• Debug using schematic tracer
• Debug using data flow window
• Debug using simulation break points