Syllabus
Course Overview
Schedule
Demo
FAQs
Trainer
Certificate
Syllabus
- Introduction to PAM4 (Pulse Amplitude Modulation with 4 Levels).
- Advantages over NRZ for achieving 64 GT/s.
- Signal integrity challenges (noise, jitter, crosstalk).
- Receiver equalization for PAM4.
- IDefinition of Flit (Flow Control Unit) Mode.
- Differences between Flit and Non-Flit modes.
- Benefits of Flit Mode (lower latency, alignment).
- Transition from Non-Flit to Flit mode.
- Introduction to PAM4 (Pulse Amplitude Modulation with 4 Levels).
- Purpose and role of FEC in Gen6.
- Error correction for PAM4 signaling.
- Impact of FEC on latency and throughput.
- Gen6 link width and lane configurations.
- Topology changes from previous generations.
- Support for multi-host and multi-root configurations.
- Header Formats: Changes in header structure.
- Deferrable MWr Request: Concept and use cases.
- Common Packet Header Fields for Flit and Non-Flit Mode.
- Flit Mode TLP Header Type Encodings.
- Trailer Size Adjustments.
- Ordered Header Categories (OHC – A, B, C, E).
- Address Translation Services (ATS) updates.
- Routing Rules for TLPs.
- Transaction Processing Hints (TPH) Rules for Flit and Non-Flit Modes.
- Packet Header (PH) Updates.
- Steering Tag for efficient routing.
- TLP Header Format for Flit Mode.
- TLP Prefix Processing (Local and End-to-End).
- Process Address Space ID (PASID) functionality.
- Segment ID Field Introduction.
- Shared Credit Pooling Mechanism.
- Updates in Data Link Control and Management State Machine (DLCMSM).
- DLLP (Data Link Layer Packet) Rules.
- DLLP Type Encodings for Gen6.
- Encoding Changes in DLLPs.
- Introduction of NOP and NOP2 DLLPs.
- Link Management DLLP Enhancements.
- New Data Link Feature DLLPs.
- Power Management DLLPs.
- Flit Mode Operations in Physical Layer.
- Power Management States: L0p and L0p Handshake using Link Management DLLP.
- L0s Updates.
- LTSSM (Link Training and Status State Machine) Updates.
- 1b/1b Encoding and Scrambling.
- Valid Encodings for Ordered Sets.
- Processing of Ordered Sets at 64 GT/s.
- Flit Mode Identification.
- Symbol Placement in 1b/1b Encoding.
- Transmit and Receive Side Operations for Flit Mode.
- Alignment at Block/Flit Level for 1b/1b Encoding.
- Gray Coding and Precoding Mechanisms.
- Decision Feedback Equalization (DFE).
- Data Stream in Flit Mode.
- FEC and Its Role in the Physical Layer.
- TLP and DLLP Bytes in Flit.
- Types of Flits (Idle, NOP, Payload).
- Implicit and Explicit Sequence Number Flits.
- Transmitter and Receiver Variables and Buffers in Flit Mode.
- Flit Replay and Retry Mechanism.
- Flit Sequencer Number Rules for Transmitter and Receiver.
- Handshake Phases:
- IDLE Flit Handshake Phase.
- Sequence Number Handshake Phase.
- Normal Flit Exchange Phase.
- Received ACK, NAK, and Discard Rules.
- Flit Replay Scheduling and Transmit Rules.
- Examples of Flit ACK/NAK/Replay Processing.
- Ordered Set Updates:
- TS0.
- Modified TS1 and TS2.
- EIOSQ and EIEOSQ.
- Half Scrambling Updates.
- Equalization Enhancements in Gen6.
- Clock Tolerance Compensation Updates.
- Alternate Protocol Negotiation.
- Retimer Enhancements.
- Improvements in Active State Power Management (ASPM).
- Support for deeper power states.
- Dynamic power scaling features.
- Updates in Message TLPs for Gen6.
- Enhanced signaling and messaging features.
- New extended capabilities introduced in Gen6.
- Modifications to existing capability structures for Flit Mode.
Course Overview
PCIe gen6 Training
The PCIe Gen6 Training provides engineers with a comprehensive understanding of the latest PCIe standard, focusing on Flit Mode, PAM4 signaling, and protocol enhancements introduced in Gen6. Participants will explore the architecture, features, and implementation details of PCIe Gen6, along with practical insights into system design and verification challenges.
By the end of the course, learners will be equipped to work confidently on cutting-edge SoC projects requiring high-bandwidth, low-latency interconnect solutions.
Schedule
| Course | PCIe Gen6 protocol training |
|---|---|
| Duration | Live training : 6 weeks eLearning : 36 hours |
| Next Batch | |
| Schedule | Saturday, Sunday, 9AM to 12PM |
| Tool | Questasim & VCS |
| Mode of training | Live training for minimum of 10 participants or corporate training eLearning with dedicated mentor for doubt clarifications |
| Fee | Live training : INR 11K + GST eLearning : INR 9K + GST |
| Assignments | 5 |
Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to standard bus protocols
- Exposure to Testbench component coding using SystemVerilog
Each session of course is recorded, missed session videos will be s
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer
Experienced Trainer
- 12 years of work experience in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
Certificate
Play Video
- 1-1 Dedicated Mentor Support
- mock interview
- Industry Standard Projects
- Support with resume update