Online VLSI Front end training for freshers (VG-FEDV)
course is a 19 weeks course structured to enable BTech, MTech, BS and MS graduates gain
skill in full breadth of VLSI front end domain. Course is offered using gotomeeting live online training sessions. Session timings are scheduled are before noon(India time), so as to be comfortable for students attending training online from USA, Europe and India.Online vlsi front end training course ensures that a fresher is prepared on all the essential aspects of VLSI front end domain including training on VLSI flow, SOC design and verification concepts, advanced digital design, Verilog, Systemverilog, essential UVM, UNIX, revision management and scripting. Course also includes training on soft skill for effective interview performance.
Lack of fundamentals in Advanced Digital Design, Analog Design and Verilog based design & verification becomes a major deterrent for freshers in finding right career opportunities. online vlsi front end training course ensures that fresher is empowered with all the essential skill set
required for various jobs in VLSI front end domain. Course is completely practical oriented with each aspect of course involving multiple hands on projects. All the courses are offered by trainers with more than 10+ years of relevant experience. Student progress is tracked using 100+ detailed assignments covering all the aspects from digital design, VLSI flow, SOC design & verification, RTL coding, Verilog, System verilog, RTL debug, UNIX, and scripting.
VLSI Design flow training covers complete ASIC flow exposure from specifications till
GDSII including Architecture, Specifications, RTL coding, lint checks, RTL
integration, connectivity checks, functional verification, synthesis, Gate
level simulations, formal equivalence checks, STA, placement and routing,
clock tree synthesis, DFT, custom layout and post silicon validation.
SOC Design and verification focus on SOC design concepts, SOC architecture,
SOC verification concepts and differences when compared to module level
Advanced digital design training focus on all the digital design concepts
including combinational logic, sequential logic, circuit design concepts,
memory types and other essential things focused in majority of fresher
interviews. Course assume minimal exposure to digital design concepts, it
starts from basic concepts till advanced concepts including clock domain
crossing, synchronizers, timing violation fixing, etc.
Verilog & RTL coding focus on teaching all Verilog language constructs from
practical usage perspective. Training involves 25+ design coding
examples focused in fresher interviews.
Systemverilog training gives fresher with required exposure to advanced
functional verification concepts. All language constructs are covered with detailed
coding examples involving more than 200 examples. Course also offers exposure to standard on-chip communication protocols and verification IP development for AXI.
RTL debug training will focus on training student with important debug concepts
including schematic tracing, RTL tracing, RTL & TB coding issues, etc.
UNIX training ensures that student gets accustomed to industry work
environment. Traning also includes exposure to Makefile, revision management
and all essential UNIX concepts.
Scripting training will focus PERL essential concepts. It will help student
gain exposure to file management, regular expressions, Object oriented PERL,
PERL modules and PERL usage in industry.
Soft skill training will prepare student on how to face interviews
effectively, right body language, etc.
COurse is also targeted for engineers working in non-VLSI domains and planning
to make career in VLSI.
Students planning to pursue complex projects after this course can do by
paying a nominal fee. Institute offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.
RTL coding, lint checks
Synthesis & STA
Gate level simulations
Power aware simulations
Placement and Routing
Post silicon validation
SOC Design and Verification concepts
SOC Architecture overview
SOC design concepts
SOC verification concepts
SOC use cases
SOC Testbench architecture
SOC Testcase coding
SOC verification differences with module verification
Advanced Digital Design concepts
Digital Design basics
sequential logic, FF, latch, counters
Refer to Advanced digital design training page for detailed course contents
Verilog for Design and verification
Verilog language constructs
Verilog design coding examples covering morethan 20 standard designs
SystemVerilog for Advanced Verification
Classes : Object Oriented Programming
Arrays, Data Types, Literals, Operators
Scheduling Semantics, Inter process Synchronization