VLSI Design and Verification training for Freshers

Online training in Verilog for Design & Verification (VG-VO) is structured to enable engineers develop their skills in full breadth of Verilog Constructs in Complex Design implementation and Directed testbench Setup. VT-VO course is targeted for both design & verification engineers who want to gain expertise in using Verilog for design & testbench development.
Course will also focus on Advanced Digital design concepts & Basic Analog design concepts. VG-VO done over 5 weeks to ensure student is completely prepared with all Verilog, Digital & Analog design concepts. It covers majority of the standard Verilog, DIgital design & Analog design questions.

Course has been framed in a way to make Verilog learning a fun and interesting activity. Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple design implementation examples and testbench setup for same, all of these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VERILOG

  • Verilog language constructs with detailed examples on each construct usage
  • Multiple Design Coding & Testbench development
  • Access to Questasim tool
  • Hands on labs & Hands on projects
  • Basic Digital Design Concepts
  • Advanced Digital Design Concepts
  • Basic Analog Design Concepts

Introduction to Verilog

  • Introduction to Verilog Course
  • Module
  • Data types
  • Data Flow
  • Procedural Blocks
  • Language Statements
  • State Machines
  • Gate Level Implementation
  • Verilog Programing Interface(& PLI)

Commonly asked Verilog Design Examples : All covered in course training

  • Flipflop (Synchronous & Asynch Reset), Latch
  • Counter-Gray code counter, modulo, ring, johnson, up counter, down counter
  • Shift register implementation
  • Half adder, full adder, multiplexer
  • Dual port memory write, read design & testbench
  • encoder, decoder, various gates
  • Primitive implementation using table, endtable
  • Pattern detector
  • Coin counter for tea vending machine
  • Traffic light controller(TLC)
  • CRC generation code
  • Watchdog timer implementation
  • Synchronous FIFO
  • Asynchronous FIFO
  • Memory implementation
  • example to showcase race condition using blocking assignments
  • system task usage: $display, $monitor, $strobe
  • PLI, VPI implementation
  • Memory controller RTL understanding, architecture understanding
  • Clock generation with Duty cycle & Jitter
  • PCIe different layer implementation
  • Interrupt Controller

Verilog for Verification

Verification of all above designs using Verilog

Course Verilog for Design & Functional Verification
Duration 6 weeks
Next Batches 21/Sep, 26/Oct, 30/Nov
Demo Session 21/Sep (9AM – 1PM)
Course Enroll 22/Sep
Freshers Full week course
Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9:30AM to 12:30PM). Flexible lab sessions for US Students.
Weekdays sessions will be focused on training on Assignment solving sessions; evaluation tests; and labs.
Students also get support on complete project flow during weekdays as well.
New batch starts Every 6 Weeks
Fee INR 8000
Tool Questasim
Mode of training Classroom training at VLSIGuru Institute(Horamavu)
Online training using live training sessions
Certificate Issued based on 50% assignment completion as criteria
Batch Size 20
Assignments 24
Trainer 12+ Years exp in RTL design & Functional verification

What are the Course Prerequisites?

Expertise on design design concepts

Does course cover practical sessions on UVM usage?

  • Each aspect of course is supported by lot of practical examples
  • Dedicated full day lab sessions to ensure student does complete testbench development from scratch

Course has started few weeks back, can I still join the course in between?

You will have option to repeat the course any time in next 1 year

Do you offer support after course completion?

  • Yes, Course fee also includes support for doubt clarification sessions even after course completion
  • You have option to mail you queries
  • Option to meet in person to clarify doubts

Course Material Shared:

  • Verilog User Guide
  • Verilog Checklist
  • Verilog Lab Examples

Target Audience:

  • MTech & BTech freshers would like to start learning directed verification
  • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
  • Engineering college faculty looking to enhance their VLSI skill set

Trainer Profile

  • 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
  • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
  • Experience of working on multiple complex module level projects
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