Online course in Systemverilog for functional verification

Online course in SystemVerilog for Functional Verification is a 12 weeks course structured to enable engineers develop their skills in full breadth of systemverilog features. VT-SVO course covers all aspects of functional verification including constrained random verification, assertion based verification and coverage driven verification. VT-SVO course has been framed to fit to every functional verification engineer requirements and also targeted for graduates aspiring to make career in VLSI Front End domain. Course approaches by teaching basic concepts to most advanced aspects of SV with relevant examples to enable easier understanding of concepts.

VT-SVO course also includes training industry standard protocols like AXI, AHB, etc, with emphasis on teaching industry standard AXI protocol and developing Verification IP for same. Course also includes 1 industry standard project. All these projects are executed from scratch with students working on complete flow starting from specification reading, feature listing down, testbench architecture creation, component coding and testcase development till verification closure using coverage and regression as verification closure criteria.

VT-SVO course also includes multiple weeks of Lab sessions to enable student put effort in doing above projects from scratch.

SystemVerilog for Advanced Verification

  • Classes : Object Oriented Programming
  • Arrays, Data Types, Literals, Operators
  • Scheduling Semantics, Inter process Synchronization
  • Processes, Threads, Tasks and Functions
  • Randomization, Constraints
  • Interface, Clocking blocks, Program Block
  • Functional Coverage
  • Assertion Based Verification
  • System Tasks & Functions
  • Compiler Directives
  • DPI

ASIC Verification Concepts

  • SoC Verification Concepts
  • Module Level Verification
  • Constrained Random Verification
  • Coverage Driven Verification
  • Directed Verification
  • Assertion Based Verification

Verification IP Development

  • AXI Protocol Concepts : Features, Signals, Timing Diagrams
  • AXI VIP Architecture Development
  • VIP Component Coding
  • AXI Slave model testcase development
  • Testcase debugging

Module(IP) Level Verification Project

  • Specification analysis
  • Verification Plan creation
  • Feature & Scenario Listing down
  • TB architecture creation
  • Building Top level verification environment
  • TB component coding and integration
  • Sanity test case and environment bring up
  • Complete test case coding
  • Building regression test suite
  • Functional coverage and code coverage analysis

Course Assignments

  • VIP Developmet for one of OCP/Wishbone/APB/Ethernet Protocols
  • Verification of PCIEx Physical Layer LTSSM FSM from scrach
  • Functional Verifcation of a complex module
Course Systemverilog for Functional Verification
Duration 12 weeks
Next Batches 21/Nov
Demo Session 21/Nov (9AM – 1PM).
Course Enroll 22/Nov
Freshers Full week course
Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9:30AM to 12:30PM). Flexible lab sessions for US Students.
Weekdays sessions will be focused on course labs, assignments and interview focused sessions.
Students also get support on complete project flow during weekdays as well.
Working professionals Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US)
8:30AM – 12:30PM (Theory session offered by trainer)
1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time.
Students will take the weekday tests and assignments from home.
New batch starts Every 6 Weeks
Fee INR 20000 +GST at 18% (Online Training)
Tool Questasim
Mode of training Classroom training at VLSIGuru Institute(Horamavu)
Online training using live training sessions
Tool Access Tool access at institute for 12 months from course start date
Certificate Issued based on 50% assignment completion as criteria
Batch Size 20
Assignments 23
Admission criteria Student need to undergo evaluation test based on basic digital and aptitude
Placement support Interview opportunity in at least 6 companies
100% job on completion of all assignments
and scoring good grade in monthly evaluation test
Trainer 12+ Years exp in RTL design & Functional verification
Content Learning Schedule(T : Course Start Date)
Systemverilog language constructs T to T+6th week
AXI Protocol and AXI VIP Development T+6 to T+7th week
Memory Controller Functional Verification T+8 to T+10th week

What are the Course Prerequisites?

  • Expertise on Verilog
  • Exposure to Testbench component coding using Verilog

Does course cover practical sessions on SystemVerilog usage?

  • Each aspect of course is supported by lot of practical examples
  • Ethernet loopback design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
  • All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
  • Dedicated full day lab sessions to ensure student does complete testbench development from scratch

Is it possible to cover so many things in 8 weeks?

  • We have done it for 23 Batches so far, next batch is no exception
  • Course requires student to spend at least 6+ hours of time a week to revise the concepts

What if I miss few sessions during course?

Each session of course is recorded, missed session videos will be shared

Course has started few weeks back, can I still join the course in between?

  • Yes, You will have option to view the recorded videos of course for the sessions missed
  • You will have option to repeat the course any time in next 1 year

Do you offer support after course completion?

  • Yes, Course fee also includes support for doubt clarification sessions even after course completion
  • You have option to mail you queries
  • Option to meet in person to clarify doubts
Systemverilog Material Access
Course material Shared over google drive consists of IEEE Manual-Labs & project code
Course page access Get login details from Admin
Assignments-Checklist-Session notes Course page
Labs Shared as part of course material and also shared every week
Gvim install & usage Youtube video shared as part of course guidelines
How to use course material Shared as part of Course material
Resume update Shared as part of Course material
Interview Questions Uploaded to course page
Labs for every week session sent as mail attachment at the end of every week

Target Audience:

  • Verification engineers looking to learn advanced verification techniques
  • MTech & BTech freshers who are well versed with Verilog, and would like to learn advanced verification
  • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
  • Engineering college faculty looking to enhance their VLSI skill set

Trainer Profile

  • 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
  • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
  • Experience of working on multiple complex module level projects
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