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VLSI Internship Overview

 Duration: 10 months internship in VLSI & Embedded Systems

  • Student will be issued training completion certificate and 1 year trainee certificate.

 Start date: 4 Batches of Internship

  • 1st batch: 24-June-2017
  • 2nd batch: 29-July-2017
  • 3rd batch: 02-Sept-2017
  • 4th batch: 14-Oct-2017

Contact: contact@vlsiguru.com  Ph: 9986194191

Course Overview:

  • Course divided in to 2 aspects
    • Learning phase
    • Application phase
  • During ‘learning phase’; Student will undergo 3 months extensive training on Advanced Digital Design, Verilog, SystemVerilog and UVM basics, standard protocols like AXI, AHB, Ethernet MAC, etc. Student will be working on multiple industry standard project as part of SV & UVM learning.
  • During ‘application phase’, Student will be working on industry standard project with trainer guidance. Same project can be used as MTech Project.

Project done as part Internship learning phase:

  • Ethernet Loopback Design Functional Verification
  • AXI VIP Development
  • Memory Controller Design Functional Verification
  • AHB UVC Development

Projects as part of Internship application phase, student can choose one of projects

  • AXI2OCP Bridge Design Functional Verification
  • Ethernet MAC Design Functional Verification
  • AXI Interconnect Design Functional Verification
  • AHB Interconnect Design Functional Verification
  • AHB2AXI Bridge Design Functional Verification
  • UART Controller Design Functional Verification
  • PRCM Design Functional Verification
  • DMA Controller Design Functional Verification

Detailed Course Content:

  1. Advanced Digital & Analog design concepts
  2. Verilog (www.vlsiguru.com/verilog-training)
  3. System Verilog(www.vlsiguru.com/system-verilog-training)
  4. UVM Essentials (www.vlsiguru.com/uvm-training)

 

Internship Overview Video:

MTech Projects & Internship

  • Given the competition in VLSI job market, it becomes essential for ME & BE students to get themselves prepared for VLSI job while they are in college.
    Below is how internship would help:
    • Helps bridge the gap between graduate academics with industry requirements.
    • Saves 6 months time spent on training after passing out from college.
    • Helps them choose right project of ME.
    • 1 year experience and internship certificate

    MTech projects are based on industry standard design & verification projects MTech internship will be targeted towards enabling student learn complete verification concepts including SV & UVM based verification.

    • Projects on IEEE standard and based design & verification using SV & UVM
    • Projects based on industry standard Protocols like AXI, AHB, USB, PCIe etc
  • VLSI Internship OverviewDuration: 10 months internship in VLSI & Embedded SystemsStudent will be issued training completion certificate and 1 year trainee certificate from SOCDV Technologies(www.socdvtech.com) Start date: 3 Batches of Internship1st batch: 28-May-2016 2nd batch: 09-Jul-2016 3rd batch: 27-Aug-2016 Contact: contact@vlsiguru.com Ph: 9986194191Course Overview:Course divided in to 2 aspects Learning phase Application phase During ‘learning phase’; Student will undergo 3 months extensive training on Advanced Digital Design, Verilog, SystemVerilog and UVM basics, standard protocols like AXI, AHB, Ethernet MAC, etc. Student will be working on multiple industry standard project as part of SV & UVM learning. During ‘application phase’, Student will be working on industry standard project with trainer guidance. Same project can be used as MTech Project. Project done as part Internship learning phase:Ethernet Loopback Design Functional Verification AXI VIP Development Memory Controller Design Functional Verification AHB UVC Development Projects as part of Internship application phase, student can choose one of projectsAXI2OCP Bridge Design Functional Verification Ethernet MAC Design Functional Verification AXI Interconnect Design Functional Verification AHB Interconnect Design Functional Verification AHB2AXI Bridge Design Functional Verification UART Controller Design Functional Verification PRCM Design Functional Verification DMA Controller Design Functional Verification Detailed Course Content:Advanced Digital & Analog design concepts Verilog (www.vlsiguru.com/verilog-training) System Verilog(www.vlsiguru.com/system-verilog-training) UVM Essentials (www.vlsiguru.com/uvm-training)
    • Internship Duration: 1 year
    • Fee : INR 16,000 excluding UVM essentials
    • INR 20,000 including UVM essentials
    • Tools : Questasim(Mentor Graphics)
    • Access to tool using remote connection
    • Certificate of course completion and experience letter

    • How internship helps?

      • Targeted to bridge gap in academics to industry
      • Exposure to Verilog, SystemVerilog and UVM including multiple industry standard projects
    • What are the Course Prerequisites?

      • Expertise on verilog Language
      • Exposure to Testbench component coding using verilog
    • Course has started few weeks back, can I still join the course in between?

      • Yes, You will have option to view the recorded videos of course for the sessions missed
      • You will have option to repeat the course any time in next 1 year
    • Do you offer support after course completion?

      • Yes, Course fee also includes support for doubt clarification sessions even after course completion
      • You have option to mail you queries
      • Option to meet in person to clarify doubts
    • Verilog course materiak
    • SV Course material
    • Digitial design material & course videos
    • UVM course material
    • Target Audience:
      • MTech & BTech freshers looling to make career in VLSI domain.
      • Engineering college faculty looking to enhance their VLSI skill set
    • Trainer Profile
      • 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
      • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
      • Experience of working on multiple complex module level projects