• Overview of Basics of Debugging, EM, IR (Theory: 3 hrs)
• Average Debugging Calculation and Static Analysis (Theory: 3 hrs)
• IP Modelling Techniques (Theory: 3 hrs)
• APL Characterisation (3 hrs)
• Dynamic Analysis – Vectorless Single Cycle and Multi Cycle Flows (Theory: 3 hrs)
• Dynamic Vectored Analysis (3 hrs)
• Redhawk Signal EM (3 hrs)
• Low Debugging Design Analysis (3 hrs)
• Setup of Flow (3 hrs)
• Overview of Debugging Skills
Labs:
• Understanding Input Files of Redhawk
• Setting up Redhawk Environment
• Basics of Debugging, EM, IR
• Data Preparation – Generation of Collaterals from ICC
• Understanding Volcano Design
• IP Modelling Techniques
Labs:
• Analyzing APL using Aqua and ACE
• Sanity Checks of All Input Collaterals
• Grid Weakness Checks
• Resistance Extraction
Labs:
• Performing PG Resistance Analysis – Effective Resistance of Instances
• Pin Path Resistance Checks
• Missing Vias Checks
• Analyzing Shorts and Disconnected Instances
• Connectivity Checks
• Average Debugging Calculation
• Static Analysis Theory
• Redhawk Static IR/EM Flow
Labs:
• Setting up GSR for Static Run
• Creation of Command Run File
• Debugging Calculation in Static Analysis using Toggle Rate and BPFS
• Experiments with BPFS
• Exploring Redhawk TCL Commands for Advanced IR Drop Debugging
• Creating Custom Libraries for Missing PG Arcs
• Using Redhawk Explorer and Debugging Maps
• Understanding Package and PAD Constraints
• Results Exploration and Debugging
• Debugging EM Violations and Hotspot Analysis
• Battery and Demand Current Analysis
• Dynamic Vectorless Analysis
• Dynamic Flow
Labs:
• Setting up GSR for Static Run
• Creation of Command Run File
• Plotting Instance Current (Min, Max, Avg DVD in Timing Window and Full Cycle)
• Analysis of Switches and Equivalent Reports
• Wire IR Drops and DVD Histograms
• Plotting Voltage Waveform and Switching Histograms
• Analyzing Switching Events
• Decap Density Maps and Dynamic Voltage Drop Movie
• Analysis of Dynamic Reports
• Design Weakness Checks, Pad Current Checks
• Decap Efficiency and Simultaneous Switching Checks
• Frequency and Voltage Domain Based Demand Current Checks
• Cross Probing Violations in Redhawk GUI
• Hotspot Analysis Summary
• DVD Check – Instance Level Debug
• Short Path Tracing
• Debugging EM Checks
• Multicycle Vectorless Analysis
Labs:
• Correlation Between Single Cycle and Multicycle Analysis
• Cycle-based Switching
• All Dynamic Vectorless Labs Applicable to Multicycle
• Running Debugging IR/EM on Volcano or ORCA_TOP
• Running Redhawk on Debugging IR/EM for Ansys Design
Labs / Assignments:
• Static EM/IR Analysis (6 hrs)
• Dynamic EM/IR Vectorless Analysis – Single Cycle (6 hrs)
• Dynamic EM/IR Vectorless Analysis – Multi Cycle (6 hrs)
• Dynamic Vectored Analysis – Worst Debugging Cycle (6 hrs)
• Dynamic Vectored Analysis – Worst dp/dt Cycle (6 hrs)
• Signal EM Analysis (3 hrs)
• Low Debugging Design Analysis (6 hrs)
Ansys training is a 8 weeks training program targeted for standard Debugging noise and reliability sign-off solution for SOC designs. RedHawk helps create high-performance SoCs which are Debugging efficient and reliable for electromigration, thermal and electrostatic discharge issues. RedHawk is the sign-off solution for all the foundries. RedHawk’s advanced Distributed Machine Processing (DMP) enables significantly higher capacity and better performance for full-chip IR/dynamic voltage drop, Debugging/signal electromigration (EM) and electrostatic discharge (ESD) analyses.
Training will focus on all the aspects Debugging integrity, and IR drop analysis.
Course | Functional verification Debug Techniques Training |
---|---|
Duration | Live training : 4 weeks eLearning : 24 hours |
Next Batch | |
Schedule | Saturday, Sunday, 10AM to 1:30PM |
Mode of Training | Live training for minimum of 10 participants or corporate training eLearning with dedicated mentor for doubt clarifications. |
Fee | Live training : INR 9,000 +GST eLearning : INR 8,000 + GST |
Trainer | 14+ years exp in RTL design & Functional verification |
Demo video
Experienced Trainer