AMBA Protocol training is structured to enable engineers gain perfection in AXI, AHB & APB protocols. Majority of designs are based on ARM architecture. All ARM architectures are based on AMBA protocols(AXI, AHB and APB), which makes it essential for every design & verification engineer to have detailed understanding of these protocols. SoC design debug and testbench component coding in most cases involves either AXI and/or AHB protocols, and also majority of interviews are focused on candidate familiarity with AXI or AHB protocol. All this makes it essential for every VLSI engineer to have good working knowledge of these protocols.
AMBA Protocol training course focuses on teaching protocol concepts, features, timing diagrams from basic to advanced for AXI4.0, AHB2.0 and APB. Course also focus on teaching protocol testbench development concepts. Student has flexibility to choose specific protocol as well.
AXI4.0 Protocol
Introduction to on-chip protocols
- Protocol overview
- AXI revisions
- AXI based system architecture
Signal descriptions
- Global signals
- Write address channel signals
- Write data channel signals
- Write response channel signals
- Read address channel signals
- Read data channel signals
- Low power interface signals
Signal Interface requirements
- Basic write and read transactions
- Relationship between channels
- Transaction structure
Transaction attributes
- Transaction types and attributes
- AXI3 memory attribute signalling
- AXI4 changes to memory attribute signalling
- Memory types
- Mismatched memory attributes
- Transaction buffering
- Access permissions
Multiple transactions
- AXI transaction identifiers
- Transaction ID
- Transaction ordering
AXI4 Ordering model
- Definition of ordering model
- Master ordering
- Interconnect ordering
- Slave ordering
- Response before final destination
Atomic accesses
- Single-copy atomicity size
- Exclusive accesses
- Locked accesses
- Atomic access signaling
AXI4 additional signaling
- QoS signaling
- Multiple region signaling
- User-defined signaling
Low-power interface
- Low power interface signals
- Low power clock control
Default signaling and Interoperability
- Interoperability principles
- Major Interface categories
- Default signal values
AXI3.0 Verification IP(VIP) Development
- VIP architecture
- VIP components
- VIP types
- Master, Slave
- Active, Passive
- VIP test scenario listing down
- VIP component coding
- Driver, Generator, Monitor, Coverage, Environment
- Interface, transaction, Slave model, assertions
- Testbench integration
- Testcase coding
- Simulations and waveform analysis
- Functional coverage analysis
- Assertion coding and analysis
Student assignment: AXI4 VIP Development
Enhance AXI3 VIP for AXI4 additional features
- QoS signaling
- Multiple region signaling
- User-defined signaling
- Low power interface
AHB5 protocol
Introduction
- About the protocol
- AHB revisions
- Operation
Signal Descriptions
- Global signals
- Master signals
- Slave signals
- Decoder signals
- Multiplexor signals
Transfers
- Basic transfers
- Transfer types
- Locked transfers
- Transfer size
- Burst operation
- Waited transfers
- Protection control
- Memory types
- Secure transfers
Bus Interconnection
- Interconnect
Address decoding
Read data and response multiplexor
Slave Response Signaling
- Slave transfer responses
Data Buses
- Data buses
- Endianness
- Data bus width
Clock and Reset
- Clock and reset requirements
Exclusive Transfers
- Introduction
- Exclusive Access Monitor
- Exclusive access signaling
- Exclusive Transfer restrictions
Atomicity
- Single-copy atomicity size
- Multi-copy atomicity
User Signaling
- User signal description
- User signal interconnect recommendations
AHB UVC Development
- UVC architecture
- UVC components
- UVC types
- Master, Slave
- Active, Passive
- UVC test scenario listing down
- UVC component coding
- Driver, Sequencer, Monitor, Coverage, Environment
- Interface, transaction, Slave model, assertions
- Testbench integration
- Testcase coding
- Simulations and waveform analysis
- Functional coverage analysis
- Assertion coding and analysis
APB Protocol
- APB protocol introduction
- Signal descriptions
- Transfers
- Operating states
Student assignment: APB UVC Development
- Develop APB UVC for master and slave
- APB master UVC validation using slave UVC
| Course | AMBA Protocol training, AXI VIP, AHB UVC and APB UVC Development | |
|---|---|---|
| Duration | 6 weeks | |
| Next Batches | 16/May | |
| Demo Session | 16/May(9AM – 1PM) | |
| Course Enrolment | 17/May | |
| Schedule | ||
| Freshers | Full week course | |
| Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9AM to 1PM). Flexible lab sessions for US Students. | ||
| Weekdays sessions will be focused on course labs, interview preparation | ||
| Students also get support on complete project flow during weekdays as well. | ||
| Working professionals | Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US) | |
| 8:30AM – 12:30PM (Theory session offered by trainer) | ||
| 1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time. | ||
| Students will take the weekday tests and assignments from home. | ||
| New batch starts | Every 10 Weeks | |
| Fee | INR 11000 + GST@18% (Classroom training) | |
| INR 12000 + GST@18% (Online training) | ||
| Tool | Questasim & VCS | |
| Mode of training | Classroom training at Institute(ORR, Banaswadi) | |
| Online training using live training sessions | ||
| Tool Access | Access to tool at institute for 12 months | |
| Certificate | Issued based on 50% assignment completion as criteria | |
| Assignments | 5 | |
| Trainer | 14+ Years exp in RTL design & Functional verification |
What are the Course Prerequisites?
- Exposure to any bus protocols like I2C, SPI, etc
- Exposure to digital design concepts
Does course cover practical sessions on protocols?
Yes. Participant will gain exposure to following aspects
- VIP development for AXI3 protocol
- UVC development for AHB2 protocol
- UVC development for APB protocol
- Analysing AXI, AHB and APB timing diagrams in simulations
- Functional coverage analysis
- Assertion coding and debugging
What if I miss few sessions during course?
Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Course Material Shared
- AXI, AHB, APB protocol specifications
- VIP/UVC code for AXI, AHB, & APB protocols
- Short notes/checklist for each protocol
Target Audience:
- Verification engineers with no prior exposure to any AMBA protocol.
- Verification engineers looking for better career opportunities, and looking to improve their profiel
- Engineering college faculty looking to enhance their VLSI skill set
Trainer Profile
- Institute has multiple trainers handing front end domain courses. Average experience of trainers is 10+ years.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
