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Advanced Digital Design Training with interview focus

      (Classroom & Online training)

Course Schedule & registration:

  • Duration:  16 Hours (2:00PM – 6:00PM on 4/Feb, 5/Feb, 11/Feb, 12/Feb)
  • Class room training and Live online Training sessions
  • Student progress tracked using Checklist & assignments
  • Fee : INR 1000 / $20
  • Registration: Mail: digital-training@vlsiguru.com Phone: 9986194191
    • Students attending in class: 9AM, 4/Feb at institute(www.vlsiguru.com/contact)
    • Students attending online, please initiate fee transfer to below account.

Account Name: VLSIGuru Training Institute

Account Number: 64211354057

Bank: State bank of Mysore, Horamavu, Bangalore

IFSC Code: SBMY0040807

 

Course Content (covers majority of questions asked in VLSI written tests and interview)

  • Each aspect below discussed using practical applications (detailed syllabus in Page No 3)
  • Numbering system
  • Karnaugh maps
  • Timing diagrams
  • Pipelining
  • Flipflop
  • Latch
  • Various types of FF’s, Latch’s
  • Various Counters (with practical applications)
  • FIFO
  • Data transfer synchronization between components
  • Race condition
  • Meta stability
  • Multiplexer, Using MUX to create various gates, FF
  • Decoder, encoder, priority decoder
  • Parity generation
  • Half adder, full adder
  • Truth table for HA, FA, Mux, counters
  • Buffer, inverter
  • PLL, VCO, clock generation
  • Generating X2, X3, X4, X1/2, X1/3, X1/4 clock frequencies
  • Clock domain crossing
  • Reset
  • Power management in SOC
  • State machines
  • Register
  • Memories
  • Synthesis
  • Predict design output
  • Gate level simulations
  • Debugging incorrect designs
  • Clock distribution
  • Active low and active high
  • PISO, SIPO
  • Comparator
  • Designing circuits for various requirements
  • CRC calculation logic
  • Pattern detector FSM
  • Interview focused questions
  • Give the circuit to extend the falling edge of the input by 2 clock pulses?
  • What are different ways multiply & Divide?

 

Target Audience:

  • BTech & MTech freshers looking for career opportunities in VLSI and Embedded System domains
  • Experienced engineers looking to enhance Digital Design advanced concepts

FAQ:  

  • How this course helps?
    • Majority of VLSI, Embedded System fresher interviews focus on digital design concepts
    • All the VLSI Designs are driven by Digital and analog design concepts.  Good fundamentals helps with quick design understanding.
  • What if few sessions missed?
    • Course is organized once every 3 months. Student can repeat with no additional fee.

Trainer Profile:

  • Sreenivas, Trainer with 12+ years of exp.

 

Detailed syllabus

  1. Numbering system
    1. Signed number
    2. Unsinged number
    3. 1’s complement
    4. 2’s complement
  2. Karnaugh maps
    1. Truth table
    2. Excitation table
  3. Timing diagrams
    1. Address bus
    2. Data bus
    3. Control signals
    4. Handshake signals
  4. Pipelining
  5. Flipflop
    1. Setup time
    2. Hold time
    3. FF Using NAND
    4. FF using NOR
    5. FF using J-K latch
    6. FF using latch
    7. How to calculate setup time, hold time
    8. SR FF to JK FF conversion
    9. DFF to TFF conversion
    10. JK FF to DFF
  6. Latch
    1. Difference between latch & Flipflop
  7. Various types of FF’s, Latch’s
  8. Counters (with practical applications)
    1. Gray counter
    2. Ring counter
    3. Johnson counter
      1. In a 3 bit Johnson counter, 2 states are unused, what are they
    4. Modulo-n counter
    5. Ripple counter
  9. FIFO
    1. Synchronous FIFO
    2. Asynchronous FIFO
    3. Practical applications of FIFO
    4. Difference between RAM & FIFO
    5. What is FIFO? How to Calculate the Depth of FIFO?
  10. Data transfer synchronization between components
    1. FIFO
    2. Handshake
  11. Race condition
    1. Show a design example with race condition
    2. How to fix race condition
    3. What is race around condition, how to fix it?
  12. Meta stability
  13. Multiplexer
    1. Use MUX to create AND, OR, NAND, NOR, XOR, XNOR
    2. Use MUX to create FF, Latch
    3. XOR to buffer
    4. XOR to Inverter conversion
    5. NAND to inverter
    6. Design 4 input NAND gate using 2 input NAND gates
    7. Design all gates using 2:1 MUX
    8. 3 input NAND gate using min no of 2 input NAND Gates
    9. 3 input NOR gate using min no of 2 input NOR Gates
    10. 3 input XNOR gate using min no of 2 input XNOR Gates
    11. How to implement a Master Slave flip flop using a 2 to 1 Mux?
    12. Design D Latch using 2:1 mux
    13. Design D Latch from SR Latch
  14. Decoder, encoder, priority decoder
  15. Parity generation
    1. Practical uses of parity generation
  16. Half adder, full adder
    1. FA using HA
  17. Truth table for HA, FA, Mux, counters
  18. Buffer, inverter
    1. Practical uses
  19. PLL, VCO, clock generation
    1. PLL LMN parameters
  20. Generating X2, X3, X4, X1/2, X1/3, X1/4 clock frequencies
  21. Clock domain crossing
    1. What are the different ways synchronize between two clock domains?
    2. Synchronizers : 2 stage, 3 stage
    3. T-FF
  22. Reset
    1. Practical uses, how reset distribution works
    2. Synchronous reset, Asynchronous reset
  23. Power management in SOC
    1. VD, PD, CD
  24. State machines
    1. Gray code encoding
    2. One-hot encoding
    3. Binary encoding
    4. Moore state machine
    5. Mealy state machine
    6. Difference between Moore and Mealy state machines
  25. Register
    1. Using FF
  26. Memories
    1. SDRAM
    2. SRAM
    3. NAND FLASH
    4. NOR FLASH
    5. How they function
    6. How they are modeled
  27. Synthesis
    1. Given RTL code, draw the synthesis diagram
  28. Predict design output
    1. Given a design with various gates and FF, draw the timing diagram
    2. Predict the output
  29. Gate level simulation
    1. What is x-prop
    2. Different causes of x-prop
    3. SDF format
    4. Different types of delays in digital circuits
      1. Propagation delay
      2. Rise delay, fall delay
  • Transmission delay
  1. How to fix setup time violation
  2. How to fix hold time violation
  3. What is multi cycle path
  4. What is false path, impact on circuit operation
  5. Why multi stage synchronizers are masked for x-prop checks
  1. Clock distribution
    1. Draw a logic to distribute clock for minimal clock latencies in various blocks of SOC
    2. How to minimize clock jitter
    3. How to reduce clock latency
    4. How clock gating works
    5. How to achieve 180 degrees phase shift
    6. Clock skew? How to reduce clock skew?
    7. What is glitch? What causes it (explain with waveform)? How to overcome it?
  2. Active low and active high
    1. Why interrupts are active low
  3. PISO, SIPO
    1. How do we achieve multiply and division using register shift
    2. How to achieve multiple by 3 using shift?
  4. Comparator
    1. Write gate logic to compare 2 8-bit signals
    2. Difference between full substractor and half substractor
    3. Implement full substractor from full adder
  5. Digital design interview questions
    1. The circle can rotate clockwise and back. Use minimum hardware to build a circuit to indicate the direction of rotation.
    2. You have two counters counting upto 16, built from negedge DFF , First circuit is synchronous and second is “ripple” (cascading), Which circuit has a less propagation delay? Why?
    3. Design a circuit for finding the 9’s complement of a BCD number using 4-bit binary adder and some external logic gates?
    4. Design a circuit that calculates square of a number
    5. CRC calculation logic
      1. Logic diagram
    6. Pattern detector FSM
    7. Give the circuit to extend the falling edge of the input by 2 clock pulses?
    8. Circuit design for various requirements