Course Overview

Advanced DFT Training – Summary

Duration: 5 months advanced program

Tools:

Mentor Graphics Tessent and Synopsys TetraMax (24*7 Tool access)

Placement Support: Institute provides placement support till candidate gets a JOB

Training Highlights:

Comprehensive training on full DFT flow including Scan, ATPG, BIST, and JTAG

Hands-on experience with Tessent tool across all DFT modules

Exposure to RTL and Gate-Level Netlist DFT implementation

Focus on simulation, test compression, and debugging techniques

Technical Coverage:

DFT Basics and Fault Types (Stuck-at, Transition Delay, etc.)

SoC Scan Architecture and Different Scan Types

ATPG DRC and Simulation Debug

DFT Diagnosis and Fault Analysis

JTAG, MemoryBIST, LogicBIST Implementations

Test Compression Techniques (TestKompress) and Hierarchical Scan Design

Hands-on Training:

Design featuring 17K+ flip-flops for real-world project simulation

Lab exercises on each stage of DFT flow (Scan Insertion to Pattern Validation)

Debugging and issue resolution from industry-level case studies

Training Delivery:

Conceptual clarity paired with practical labs

Delivered by experienced industry professionals

Program Highlights:

Complete DFT training from RTL to Gate-Level flows

Real-time projects and issue debugging using Mentor Tessent

Focused on industry practices and tool proficiency

Institute Info:

Offered by VLSIGuru, established in 2012

Trained over 10,000+ students

Affordable in-class training in Bangalore

Online training available for students outside Bangalore

Detailed overview:

The Advanced DFT course is a 5-month industry-aligned program providing in-depth exposure to the entire DFT flow. It covers critical testability design techniques such as Scan Insertion, ATPG, Test Compression, BIST (Memory and Logic), and JTAG. Participants gain practical experience with MentorGraphics Tessent tools across all major stages of the DFT flow. Real-time projects and labs prepare students to handle DFT challenges in both RTL and Gate-Level designs, making them job-ready for DFT roles in top semiconductor companies.

Advanced DFT(Design for Testability) course is a 5 months course providing in-depth exposure to entire DFT flow including SCAN, compression, ATPG, simulations, JTAG and BIST techniques to add testability to the Hardware design. Participants will get hands on exposure to Tessent tool for all the aspects of DFT flow.

DFT Training focused on all aspects of testability flow including DFT basics, various fault types, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.

Highlights:

Design with 17K+ flip flops

Exposure to all the aspects of flow both at RTL level and gate level netlist

Multiple lab exercises on each aspects of the flow

Exposure to issues faced in industry level project and how to resolve those issues