VLSI functional verification is a 50+ hours course covering all the aspects of Verilog, SV and UVM. It includes both theoretical and use case implementation
for all SV and UVM language constructs.

Course includes collection of important questions in all SV & UVM topics, mostly questions asked in product company interviews. Course is meant for those trying for product company placements.

Course highlights

• Covering 1200+ questions on Verilog, SV, UVM
  • Mostly coding based questions
• Questions based on TB component development
• Questions based on features listing down, test plan development, testbench architecture
• Questions based on test case coding, sequence coding
• Coding by referring to timing diagram
• Debugging based questions
• Design bug reporting and how to fix based questions
• Analyze the given code, how to find errors in the code
• Timing diagram drawing questions

VLSI functional verification is a 50+ hours course covering all the aspects of Verilog, SV and UVM. It includes both theoretical and use case implementation
for all SV and UVM language constructs.

Course includes collection of important questions in all SV & UVM topics, mostly questions asked in product company interviews. Course is meant for those trying for product company placements.

Course highlights

• Covering 1200+ questions on Verilog, SV, UVM
  • Mostly coding based questions
• Questions based on TB component development
• Questions based on features listing down, test plan development, testbench architecture
• Questions based on test case coding, sequence coding
• Coding by referring to timing diagram
• Debugging based questions
• Design bug reporting and how to fix based questions
• Analyze the given code, how to find errors in the code
• Timing diagram drawing questions

Experienced Trainer

• 10+ years of rich experience of working on scripting using PERL, TCL, SHELL & PYTHON.
• Experience of implemeting automation at different stages of project flow suing PERL, TCL & SHELL.

Target Audience:

• Every engineer who wants to utilize scripting to get smarter with work. Ex: A work manually done for 3-4 hours, could be done in 10-15 mins using intelligent scripting.
• Every engineer who has repetetive work on daily basis, and would like to automate the same. Time can be better utilized on learning more interesting things.
• Engineering college faculty looking to enhance their VLSI skill set