VLSI functional verification is a 50+ hours course covering all the aspects of Verilog, SV and UVM. It includes both theoretical and use case implementation

for all SV and UVM language constructs.

Course includes collection of important questions in all SV & UVM topics, mostly questions asked in product company interviews. Course is meant for those trying for product company placements.

Course highlights

Covering 1200+ questions on Verilog, SV, UVM

Mostly coding based questions

Questions based on TB component development

Questions based on features listing down, test plan development, testbench architecture

Questions based on test case coding, sequence coding

Coding by referring to timing diagram

Debugging based questions

Design bug reporting and how to fix based questions

Analyze the given code, how to find errors in the code

Timing diagram drawing questions