Overview

VLSI Front end training for Experienced Engineers (VG-FEDV) course is a 17 weeks course structured to enable experienced engineers gain expertise in functional verification. Majority cases, engineers does not get the hands on exposure to SV & UVM based testbench development, most of times goes in testcase coding and debug, leaving with very minimal SV & UVM expertise. This course is targeted for such engineers, to enable them get hands on exposure to complete Testbench development using SV & UVM.

Training includes more than 40+ assignments covering various aspects of Systemverilog, AXI Protocol, AXI VIP Development, Memory Controller verification, UVM constructs, AHB Protocol, AHB UVC Development and AHB Interconnect functional verification. All the aspects of the course are covered using practical examples. Systemverilog training involves more than 250+ examples covering all the aspects of Systemverilog. UVM training involves more than 100+ examples. All the examples and projects are developed from scratch as part of training sessions.

Syllabus

SystemVerilog for Advanced Verification

  • Classes : Object Oriented Programming
  • Arrays, Data Types, Literals, Operators
  • Scheduling Semantics, Inter process Synchronization
  • Processes, Threads, Tasks and Functions
  • Randomization, Constraints
  • Interface, Clocking blocks, Program Block
  • Functional Coverage
  • Assertion Based Verification
  • System Tasks & Functions
  • Compiler Directives
  • DPI

Verification IP Development

  • AXI Protocol Concepts : Features, Signals, Timing Diagrams
  • AXI VIP Architecture Development
  • VIP Component Coding
  • AXI Slave model test case development
  • Test Case debugging

ASIC Verification Concepts

  • SoC Verification Concepts
  • Module Level Verification
  • Constrained Random Verification
  • Coverage Driven Verification
  • Directed Verification
  • Assertion Based Verification

Industry Standard Project : Memory Controller Functional Verification

  • Reading Specification | Feature listing down | Scenario Listing down
  • Functional coverage listing down | Coverage Implementation
  • Testplan creation | Testbench architecture development
  • Testbench component coding | Testcase coding
  • Sanity testcase debug | Regression Setup | Regression Debug
  • Verification closure using Regression, Functional & Code coverage

UVM

  • UVM Base classes
  • UVM Messaging
  • Config db, resource db, factory
  • Sequences
  • UVM Testbench Architecture
  • AHB2.0 Protocol | AHB UVC development
  • AHB Interconnect functional verification

Course Assignments

40+ detailed assignments covering all aspects of SV & UVM.

Schedule & Fee

Course VLSI Front End Training for Experienced
Duration 17 weeks
Next Batch 05/Jan, 16/Feb, 30/Mar
Demo Session 05/Jan (9:00AM – 12:30PM)
Course Enrol 06/Jan
Schedule Both Saturday & Sunday(8:30AM – 4:00PM India time)
8:30AM – 12PM (Trainer led theory and lab sessions)
1PM to 4PM (Mentor guided lab & assignment solving sessions)
New batch starts every 6 weeks
Fee INR 29500 (Classroom Training)
INR 36000 (Online Training)
Tool Questasim
Mode of training Classroom training at VLSIGuru Institute(Horamavu)
Online training using live training sessions
Tool Access 24X7 access using VPN (Charged per month basis)
Certificate Issued based on 50% assignment completion as criteria
Admission criteria Student need to undergo evaluation test based on Verilog Digital Design VLSI Technology and Aptitude
Assignments 40
Trainer 12+ Years exp in RTL design & Functional verification

FAQs

What are the Course Prerequisites?

  • Expertise on Verilog programming

My college curriculum covers most of these topics, why should I opt for this course?

  • Course content covered in college(Btech/Mtech) curriculum is mostly theoretical and does not cover practical aspects. This course helps address that gap.

Does course cover practical sessions on SystemVerilog usage?

  • Each aspect of course is supported by lot of practical examples
  • Ethernet loopback design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
  • All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
  • Dedicated full day lab sessions to ensure student does complete testbench development from scratch

Is it possible to cover so many things in 17 weeks?

  • We have done it for 35 Batches so far, next batch is no exception
  • Course requires student to spend at least 6+ hours of time a week to revise the concepts

What if I miss few sessions during course?

  • Each session of course is recorded, missed session videos will be shared

Course has started few weeks back, can I still join the course in between?

  • Yes, You will have option to view the recorded videos of course for the sessions missed
  • You will have option to repeat the course any time in next 1 year

Do you offer support after course completion?

  • Yes, Course fee also includes support for doubt clarification sessions even after course completion
  • You have option to mail your queries
  • Option to meet trainer in person to clarify doubts

Course Material

Course Material Shared:

  • Verilog course material, assignments, labs
  • SV quick notes, IEEE manual
  • SV Checklist
  • SV Lab Examples
  • AXI VIP Code
  • Course Assignments
  • Ethernet loopback design Testbench Code
  • UNIX course material
  • PERL Scripting course material

Audience

Target Audience:

  • VLSI Engineers looking to gain expertise in SV & UVM based functional verification

Trainer

  • Trainer Profile
    • 12+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
    • Experience of working on functional verification of Multiple Complex SOCs, multiple Subsystems
    • Experience of working on multiple complex module level projects

Overview Video

Course Certificate