VLSI Design and Verification training for Freshers

  • VLSI Front end training for freshers (VG-FEDV) course is a 19 weeks course structured to enable BTech, MTech freshers gain skill in full breadth of VLSI front end domain. VLSI front end training ensures that a fresher is prepared on all the essential aspects of VLSI front end domain including training on VLSI flow, SOC design and verification concepts, advanced digital design, Verilog, Systemverilog, essential UVM, UNIX, revision management and scripting. Course also includes training on soft skill for effective interview performance.

    Lack of fundamentals in Advanced Digital Design, Analog Design and Verilog based design & verification becomes a major deterrent for freshers in finding right career opportunities. Online VLSI Front end training course ensures that fresher is empowered with all the essential skill set required for various jobs in VLSI front end domain. Course is completely practical oriented with each aspect of course involving multiple hands on projects. All the courses are offered by trainers with more than 10+ years of relevant experience. Student progress is tracked using 100+ detailed assignments covering all the aspects from digital design, VLSI flow, SOC design & verification, RTL coding, Verilog, System verilog, RTL debug, UNIX, and scripting.

    VLSI Design flow training covers complete ASIC flow exposure from specifications till GDSII including Architecture, Specifications, RTL coding, lint checks, RTL integration, connectivity checks, functional verification, synthesis, Gate level simulations, formal equivalence checks, STA, placement and routing, clock tree synthesis, DFT, custom layout and post silicon validation.

    SOC Design and verification focus on SOC design concepts, SOC architecture, SOC verification concepts and differences when compared to module level verification.

    Advanced digital design training focus on all the digital design concepts including combinational logic, sequential logic, circuit design concepts, memory types and other essential things focused in majority of fresher interviews. Course assume minimal exposure to digital design concepts, it starts from basic concepts till advanced concepts including clock domain crossing, synchronizers, timing violation fixing, etc.

    Verilog & RTL coding focus on teaching all Verilog language constructs from practical usage perspective. Training involves 25+ design coding examples focused in fresher interviews.

    Systemverilog training gives fresher with required exposure to advanced functional verification concepts. All language constructs are covered with detailed coding examples involving more than 200 examples. Course also offers exposure to standard on-chip communication protocols and verification IP development for AXI.

    RTL debug training will focus on training student with important debug concepts including schematic tracing, RTL tracing, RTL & TB coding issues, etc.

    UNIX training ensures that student gets accustomed to industry work environment. Traning also includes exposure to Makefile, revision management and all essential UNIX concepts.

    Scripting training will focus PERL essential concepts. It will help student gain exposure to file management, regular expressions, Object oriented PERL, PERL modules and PERL usage in industry.

    Soft skill training will prepare student on how to face interviews effectively, right body language, etc.

    Course is also targeted for engineers working in non-VLSI domains and planning to make career in VLSI.

    Students planning to pursue complex projects after this course can do by paying a nominal fee. Institute offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.

    • VLSI Flow

      • Specification
      • RTL coding, lint checks
      • RTL integration
      • Connectivity checks
      • Functional Verification
      • Synthesis & STA
      • Gate level simulations
      • Power aware simulations
      • Placement and Routing
      • DFT
      • Custom layout
      • Post silicon validation
    • SOC Design and Verification concepts

      • SOC Architecture overview
      • SOC design concepts
      • SOC verification concepts
      • SOC Components
      • SOC use cases
      • SOC Testbench architecture
      • SOC Test Case coding
      • SOC verification differences with module verification
    • Advanced Digital Design concepts

      • Digital Design basics
      • combinational logic
      • sequential logic, FF, latch, counters
      • Memories
      • Refer to Advanced digital design training page for detailed course contents
    • Verilog for Design and verification

      • Verilog language constructs
      • Verilog design coding examples covering more than 20 standard designs
    • SystemVerilog for Advanced Verification

      • Classes : Object Oriented Programming
      • Arrays, Data Types, Literals, Operators
      • Scheduling Semantics, Inter process Synchronization
      • Processes, Threads, Tasks and Functions
      • Randomization, Constraints
      • Interface, Clocking blocks, Program Block
      • Functional Coverage
      • Assertion Based Verification
      • System Tasks & Functions
      • Compiler Directives
      • DPI
    • Verification IP Development

      • AXI Protocol Concepts : Features, Signals, Timing Diagrams
      • AXI VIP Architecture Development
      • VIP Component Coding
      • AXI Slave model test case development
      • Test Case debugging
    • ASIC Verification Concepts

      • SoC Verification Concepts
      • Module Level Verification
      • Constrained Random Verification
      • Coverage Driven Verification
      • Directed Verification
      • Assertion Based Verification
    • Essential UVM

      • UVM Base classes
      • UVM Messaging
      • Config db, resource db, factory
      • Sequences
      • UVM Testbench Architecture
      • UVC development for APB protocol
    • RTL Debug

      • Schematic tracing
      • RTL tracing
      • FIxing RTL and TB syntax and logical errors
    • UNIX

      • Shells
      • File and directory management
      • User administration
      • Environment variables
      • Commonly used commands
      • Shell scripting basics
      • SEd and AWK
      • Revision management
      • Makefiles
    • PERL/Python Scripting

      • PERL Interpreter
      • Variables
      • File management
      • Subroutines
      • Regular expressions
      • Object oriented PERL
      • PERL modules
    • Soft Skill Training

      • Facing interviews effectively
      • industry work culture
      • Group discussions
    • Course Assignments

      • 100+ detailed assignments covering all aspects from VLSI Flow, SOC Design, Verilog, Advanced digital design, System verilog, AXI protocol, VIP Development, RTL debug, UNIX and PERL scripting.
  • Course VLSI Front End Training for Freshers
    Duration 19 weeks
    Next Batch 13/Oct
    Demo Session 13/Oct (8:30AM - 12:30PM)
    Course Enrollment 14/Oct
    Freshers Full week course
    Saturday & Sunday(8:30AM - 4:30PM India time. Monday to Friday(9:30AM to 12:30PM). Flexible lab sessions for US Students.
    Weekdays sessions will be focused on training on Digital Design - UNIX - Verilog labs - Scripting and Aptitude.
    Students also get support on complete project flow during weekdays as well.
    Working professionals Saturday & Sunday(8:30AM - 4:30PM India time. Flexible timings for students attending online from US)
    8:30AM - 12:30PM (Theory session offered by trainer)
    1PM - 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time.
    Students will take the weekday tests and assignments from home.
    New batch starts Every 6 Weeks
    Fee INR 36000 (all inclusive) (Classroom training)
    INR 45000 (Online training)
    Tool Questasim & VCS
    Mode of training Classroom training at Institute(Banaswadi)
    Online training using live training sessions
    Tool Access Student can access tool at institute 24X7
    VPN access 24X7 access to tool using VPN (charged on top of course fee)
    Certificate Issued based on 50% assignment completion as criteria
    Admission criteria Student need to undergo evaluation test based on Verilog Digital Design VLSI Technology and Aptitude
    Assignments 50
    Evaluation tests 70(student will take one evaluation test once every 2 days; followed by discussion).
    Trainer 12+ Years exp in RTL design & Functional verification

    Content Learning Schedule(T : Course Start Date)
    Advanced Digital Design Concepts T to T+6th week
    VLSI Design Flow T to T+6th week
    Verilog for Design and Verification T to T+6th week
    Systemverilog for functional verification T+6 to T+16th week
    UNIX T+6 to T+16th week
    SOC Verification Concepts T+6 to T+16th week
    UVM Essentials T+14 to T+19th week
    Python Scripting T+16 to T+19th week
    Softskill Training T+19th week

    Weekly learning schedule
    Day Content
    Saturday 8 hours of training & labs
    Sunday 8 hours of training & labs
    Monday revision of topics covered during Saturday & Sunday
    Tuesday Student presentations & group discussion
    Wednesday Softskill training & Mock interviews
    Thursday Digital design & Aptitude training
    Friday Break
    • What are the Course Prerequisites?

      • Expertise to C programming
      • Exposure to Digital design basics
    • My college curriculum covers most of these topics, why should I opt for this course?

      • Course content covered in college(Btech/Mtech) curriculum is mostly theoretical and does not cover practical aspects. This course helps address that gap.
    • Does course cover practical sessions on SystemVerilog usage?

      • Each aspect of course is supported by lot of practical examples
      • Ethernet loopback design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
      • All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
      • Dedicated full day lab sessions to ensure student does complete testbench development from scratch
    • Is it possible to cover so many things in 19 weeks?

      • We have done it for 30 Batches so far, next batch is no exception
      • Course requires student to spend at least 6+ hours of time a week to revise the concepts
    • What if I miss few sessions during course?

      • Each session of course is recorded, missed session videos will be shared
    • Course has started few weeks back, can I still join the course in between?

      • Yes, You will have option to view the recorded videos of course for the sessions missed
      • You will have option to repeat the course any time in next 1 year
    • Do you offer support after course completion?

      • Yes, Course fee also includes support for doubt clarification sessions even after course completion
      • You have option to mail your queries
      • Option to meet trainer in person to clarify doubts
  • Course Material Shared:
    • Verilog course material, assignments, labs
    • SV quick notes, IEEE manual
    • SV Checklist
    • SV Lab Examples
    • AXI VIP Code
    • Course Assignments
    • Ethernet loopback design Testbench Code
    • UNIX course material
    • PERL Scripting course material
    Students enrolled for the course(Log in to youtube using gmail Id to view below videos):
    Click here to view Course Page access video
    Click here to view Questasim usage video
    Click here to view VCS Usage video
    Click here to view GVIM editor video
    Student will get access to assignments, labs, session notes, interview questions, sample resumes on course page.
  • Target Audience:
    • MTech & BTech freshers planning to make career in VLSI Front end domain
    • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
    • Engineering college faculty looking to enhance their VLSI skill set
  • Trainer Profile
    • 12+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
    • Experience of working on functional verification of Multiple Complex SOCs, multiple Subsystems
    • Experience of working on multiple complex module level projects