UVM & OVM For Functional Verification

  • UVM for Functional Verification training (VG-UVM) course is a 7 weeks course structured to enable engineers develop skills in full breadth of UVM features in complex testbench development. UVMTraining course is targeted towards engineers looking to explore advanced functional verification techniques involving advanced methodology concepts like factory, databases and register layer. The course is targeted for engineers with all experience levels, starting from a BE, ME fresher to experienced engineers. UVM Training course is also targeted for engineers working in non-VLSI domains and planning to switch in to VLSI. Learning starts from basic examples to complex testbench development coding, to ensure a smooth learning curve.

    UVM Training course is divided in to 3 aspects, covering language constructs, industry standard protocols(AMBA AHB, APB), UVC development for these protocols and multiple industry standard projects with complete flow starting from specification reading till functional verification closure using regression, functional and code coverage as closing criteria. Institute also offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.

    UVM constructs arelearnt using more than 150+ detailed examples covering all aspects of UVM starting from base clases, uvm_root, messaging classes, policy classes, factory, configuration, resource data bases, TLM1.0, TLM2.0, sequences, sequence libraries, layered sequences, virtual sequences and sequencers, event, barrier pools and various advanced concepts like register layer, etc.AHB Interconnect design is used as a reference example to learn all above aspects of UVM.These examples cover more than 90% of questions asked in VLSI interviews.

    UVM Training course also covers multiple hands-on verification projects based on AHB, APB, AHB Interconnect And USB2.0 core. Learning starts from simple projects like AHB UVC development to complex design verification projects involving Functional verification of USB2.0 core using SV & UVM. All these projects are done from scratch. Course curriculum also ensures that student also does these projects hands-on with trainer guidance as part of dedicated lab sessions.

    UVM Training course also involves 25+ detailed assignments (20+ assignments on UVM language, 2 assignments on protocols, 2 on UVC development, and 3 on industry standard projects). These assignments are prepared by industry experts covering all aspects of SV from language constructs, protocols and multiple industry standard projects. Student gets to work on these assignments with complete guidance from trainers. Student progress is tracked using completion of assignments as a sole criteria. Student is offered with multiple (more than 10+) interview opportunities based on performance in assignments.

    Below is salient features of UVM for Functional Verification training course.
    • UVM language constructs learning using 150+ detailed examples
    • UVC development for AHB and APB protocols
    • AHB Int
    • 25+ detailed assignments covering all aspects of SV, AXI, APB, and Memory controller project
    • 24X7 tool access through VPN
    • Verification Methodologies: UVM & OVM

      • AHB Interconnect verifiation project used as reference design to learn UVM & OVM
      • AHB Interconnect will be verified from scratch while teaching all aspects of UVM
      • UVM/OVM TB Architecture
      • UVM Class Library, Macros, Utilities
      • UVM Factory, Synchronization, Containers, Policies
      • UVM Components, Comparators, Sequences, Sequencers
      • Stimulus Modeling, Sequences & Sequencers
      • Creating UVCs and Environment
      • Simulation Phases
      • TLM Overview, Components
      • Configuring TB Environment
      • Register Layer, Configuration DB & Resource DB
      • Connecting multiple UVCs
      • Creating TB infrastructure
    • AHB UVC Development

      • AHB Protocol : Features, Signals, Timing Diagrams
      • AHB UVC Architecture
      • AHB UVC Component Coding
      • AHB UVC Seqeunce & Test Development
    • AHB Interconnect Functional Verification

      • AHB Interconnect Testbench Architecture
      • AHB UVC & APB UVC in Interconnect Testbench setup
      • Verification Component Coding
      • Testcase & virtual sequence Development & Debug
    • USB2.0 Register Layer

      • Listing down registers
      • Creating Register Model
      • Integrating Register Model in to Testbench
      • Using Register Model to create tests
      • Using Register Model in scoreboard
    • USB20 Core Functional Verification

      • Specification Reading, Feature Listing, Scenario Listing
      • TB architecture creation
      • Building Top level verification environment
      • TB component coding and integration
      • Sanity test case and environment bring up
      • Testcase & Sequence coding
      • Building regression test suite
      • Functional coverage and code coverage analysis
    • Course Assignments

      • UVC Development for AXI Protocol
      • PCIe LTSSM FSM Verification
      • Register Model Development for SPI Core
  • Course UVM Training in Functional Verification
    Duration 7 weeks
    Next Batch 15/Sep
    Demo Session 15/Sep (9:30AM - 1:30PM)
    Registration 16/Sep
    Schedule Both Saturday & Sunday (8:00AM - 3:30PM IST)
    8:00AM to 12PM (Trainer led sessions covering theory and labs)
    12:30PM to 3:30PM (Mentor guided sessions covering labs assignments and doubt clarifications). Online students from US will get support in different time.
    Course repeats Every 8 Weeks
    Fee INR 12000 (all inclusive) (Classroom training)
    INR 15000 (all inclusive) (Online training)
    Tool Questasim & VCS
    Mode of training Classroom training at VLSIGuru Institute(Horamavu)
    Online training using live training sessions
    Tool Access 24X7 access using VPN (Charged on top of course fee)
    Certificate Issued based on 50% assignment completion as criteria
    Batch Size 20
    Assignments 20
    Admission criteria Student need to undergo evaluation test based on verilog & SV
    Placement support Interview opportunity in at least 6 companies
    100% job on completion of all assignments
    and scoring good grade in monthly evaluation test
    Trainer 12+ Years exp in RTL design & Functional verification
    • What are the Course Prerequisites?

      • Expertise on SystemVerilog Language
      • Exposure to Testbench component coding using SystemVerilog
    • Does course cover practical sessions on UVM usage?

      • Each aspect of course is supported by lot of practical examples
      • AHB Interconnect is reference design from Session#1 towards implementing and learning different UVM aspects
      • All UVM course examples, AHB UVC, AHB Interconnect and USB2.0 Core Verification environment implemented from scratch as part of sessions
      • Dedicated full day lab sessions to ensure student does complete testbench development from scratch
    • Is it possible to cover so many things in 9 weeks?

      • We have done it for 23 Batches so far, next batch is no exception
      • Course requires student to spend at least 6+ hours of time a week to revise the concepts
    • What if I miss few sessions during course?

      • Each session of course is recorded, missed session videos will be shared
    • Course has started few weeks back, can I still join the course in between?

      • Yes, You will have option to view the recorded videos of course for the sessions missed
      • You will have option to repeat the course any time in next 1 year
    • Do you offer support after course completion?

      • Yes, Course fee also includes support for doubt clarification sessions even after course completion
      • You have option to mail you queries
      • Option to meet in person to clarify doubts
  • UVM Material Access
    Course material Shared over google drive consists of UVM userguide-Labs & project codes for AHB & AHB Interconnect
    Course page access Get login details from Admin
    Assignments-Checklist-Session notes Course page
    Labs Shared as part of course material
    Tool access VPN
    Tool usage video Youtube video shared as part of course guidelines
    Gvim install & usage Youtube video shared as part of course guidelines
    How to run UVM TB using questasim Youtube video shared as part of course guidelines
    How to use course material Share as part of Course material
    Resume update Share as part of Course material
    Session Notes Uploaded to the course page
    Interview Questions Uploaded to course page
    Labs for every week session sent as mail attachment at the end of every week
    Students enrolled for the course(Log in to youtube using gmail Id to view below videos):
    Click here to view how to run UVM TB using Questasim video
    Click here to view Questasim usage video
    Click here to view VCS Usage video
    Click here to view GVIM editor video
    Student will get access to UVM assignments, labs, session notes, interview questions, and sample resumes on course page.
  • Target Audience:
    • Verification engineers looking to learn advanced verification techniques
    • MTech & BTech freshers who are well versed with SV, and would like to learn advanced verification
    • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
    • Engineering college faculty looking to enhance their VLSI skill set
  • Trainer Profile
    • 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
    • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
    • Experience of working on multiple complex module level projects