VLSI Training in Functional Verification

  • VLSI Online Training in Functional Verification (VG-VTO) course is structured to enable engineers develop their skills in full breadth of SystemVerilog, UVM & OVM features in complex testbench development. VLSI Training course is targeted for verification engineers with Verilog based functional verification expertize and would like to explore SystemVerilog, UVM & OVM based verification. Every aspect of course is supported with detailed examples to enable easier & quicker understanding. Course also covers multiple industry standard projects based on AXI, AHB and Memory Controller. All projects are executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VG-VTO.

    • Systemverilog Training, UVM Training
    • AXI3.0 Protocol, AXI VIP Development
    • Memory Controller Functional Verification
    • UVM & OVM Language Constructs with with detailed examples
    • AHB Protocol, AHB UVC development & AHB I/C functional verification
    • Register layer development for USB2.0
    • SystemVerilog for Advanced Verification

      • Classes : Object Oriented Programming
      • Arrays, Data Types, Literals, Operators
      • Scheduling Semantics, Inter process Synchronization
      • Processes, Threads, Tasks and Functions
      • Randomization, Constraints
      • Interface, Clocking blocks, Program Block
      • Functional Coverage
      • Assertion Based Verification
      • System Tasks & Functions
      • Compiler Directives
      • DPI
    • ASIC Verification Concepts

      • SoC Verification Concepts
      • Module Level Verification
      • Constrained Random Verification
      • Coverage Driven Verification
      • Directed Verification
      • Assertion Based Verification
    • Verification IP Development

      • AXI Protocol Concepts : Features, Signals, Timing Diagrams
      • AXI VIP Architecture Development
      • VIP Component Coding
      • AXI Slave model testcase development
      • Testcase debugging
    • Module(IP) Level Verification Project

      • Projects executed: Memory Controller (or) Ethernet MAC (or) DMA Controller (or) AXI2OCP Bridge (or) AXI2AHB Bridge (or) AHB2APB (or) USB Core (or) AXI Interconnect (or) AHB Interconnect (or) a project of similar complexity
      • Specification analysis
      • Verification Plan creation
      • Feature & Scenario Listing down
      • TB architecture creation
      • Building Top level verification environment
      • TB component coding and integration
      • Sanity test case and environment bring up
      • Complete test case coding
      • Building regression test suite
      • Functional coverage and code coverage analysis
    • Verification Methodologies: UVM & OVM

      • AHB Interconnect verifiation project used as reference design to learn UVM & OVM
      • AHB Interconnect will be verified from scratch while teaching all aspects of UVM
      • UVM/OVM TB Architecture
      • UVM Class Library, Macros, Utilities
      • UVM Factory, Synchronization, Containers, Policies
      • UVM Components, Comparators, Sequences, Sequencers
      • Stimulus Modeling, Sequences & Sequencers
      • Creating UVCs and Environment
      • Simulation Phases
      • TLM Overview, Components
      • Configuring TB Environment
      • Register Layer, Configuration DB & Resource DB
      • Connecting multiple UVCs
      • Creating TB infrastructure
    • AHB UVC Development

      • AHB Protocol : Features, Signals, Timing Diagrams
      • AHB UVC Architecture
      • AHB UVC Component Coding
      • AHB UVC Seqeunce & Test Development
    • AHB Interconnect Functional Verification

      • AHB Interconnect Testbench Architecture
      • AHB UVC & APB UVC in Interconnect Testbench setup
      • Verification Component Coding
      • Testcase & virtual sequence Development & Debug
      • Sanity test case and environment bring up
      • Testcase & Sequence coding
      • Building regression test suite
      • Functional coverage and code coverage analysis
    • Course Assignments

      • VIP Developmet for one of OCP/Wishbone/APB/Ethernet Protocols
      • Verification of PCIEx Physical Layer LTSSM FSM from scrach
      • Functional Verifcation of a complex module
      • UVC Development for AXI Protocol
      • PCIe LTSSM FSM Verification
      • Register Model Development for SPI Core
  • Course VLSI Front End Training for Experienced
    Duration 17 weeks
    Next Batch 08/Sep
    Demo Session 08/Sep (8:30AM - 12:00PM)
    Course Enrol 09/Sep
    Schedule Both Saturday & Sunday(8:30AM - 4:00PM India time)
    8:30AM - 12PM (Trainer led theory and lab sessions)
    1PM to 4PM (Mentor guided lab & assignment solving sessions)
    New batch starts every 5 weeks
    Fee INR 36000 (Online Training)
    Tool Questasim
    Mode of training Classroom training at VLSIGuru Institute(Horamavu)
    Online training using live training sessions
    Tool Access 24X7 access using VPN (Charged per month basis)
    Certificate Issued based on 50% assignment completion as criteria
    Admission criteria Student need to undergo evaluation test based on Verilog Digital Design VLSI Technology and Aptitude
    Assignments 40
    Trainer 12+ Years exp in RTL design & Functional verification
    • What are the Course Prerequisites?

      • Expertise on Verilog
      • Exposure to Testbench component coding using Verilog
    • Does course cover practical sessions on SystemVerilog usage?

      • Each aspect of course is supported by lot of practical examples
      • Ethernet loopback design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
      • All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
      • Dedicated full day lab sessions to ensure student does complete testbench development from scratch
    • Is it possible to cover so many things in 8 weeks?

      • We have done it for 23 Batches so far, next batch is no exception
      • Course requires student to spend at least 6+ hours of time a week to revise the concepts
    • What if I miss few sessions during course?

      • Each session of course is recorded, missed session videos will be shared
    • Course has started few weeks back, can I still join the course in between?

      • Yes, You will have option to view the recorded videos of course for the sessions missed
      • You will have option to repeat the course any time in next 1 year
    • Do you offer support after course completion?

      • Yes, Course fee also includes support for doubt clarification sessions even after course completion
      • You have option to mail you queries
      • Option to meet in person to clarify doubts
  • Course Material Shared:
    • SV quick notes, IEEE manual
    • SV Checklist
    • SV Lab Examples
    • AXI VIP Code
    • Ethernet loopback design Testbench Code
    • Memory controller testbench code

    • UVM User Guide
    • UVM Checklist
    • UVM Lab Examples
    • AHB UVC Code
    • AHB Interconnect Testbench Code
    • SPI Register Layer code
    • USB2.0 Core testbench Code
  • Target Audience:
    • Verification engineers looking to learn advanced verification techniques
    • MTech & BTech freshers who are well versed with Verilog, and would like to learn advanced verification
    • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
    • Engineering college faculty looking to enhance their VLSI skill set
  • Trainer Profile
    • 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
    • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
    • Experience of working on multiple complex module level projects