USB3.0 Technology(Protocol) Training
Verilog for Design and functional verification
Online Training in SystemVerilog for Functional Verification is structured to enable engineers to develop their skills in full breadth of systemverilog features. VT-SVO course covers all aspects of functional verification including constrained random verification, assertion based verification and coverage driven verification. VT-SVO course has been framed to fit to every functional verification engineer requirements and also targeted for graduates aspiring to make career in VLSI Front End domain. Course approaches by teaching basic concepts to most advanced aspects of SV with relevant examples to enable easier understanding of concepts.
Custom Layout Training
Custom layout training is 6 months course targeted for experienced engineers, BTech, BE, MTech, ME and diploma graduates planning to make career as a layout design engineer in various aspects of layout including analog layout, memory layout, standard cell layout and io layout. Custom layout design course ensures that a fresher/experienced engineer is prepared on all the essential aspects of Custom layout including ASIC flow, VLSI Design flow, Digital Design concepts, CMOS basics, FinFET basics, various memory architectures, Standard cell, IO's and detailed analog layout techniques. Course also includes training on UNIX, revision management, scripting and soft skill for effective interview performance.
Majority of graduates lack good foundation in digital and analog design concepts, make them under prepared for industry requirements. Custom layout training will enable the candidate for job opportunities within 3 months from the start of course. Complete 6 months training ensures that the candidate is an expert in the domain.
Course includes 20+ detailed labs & assignments covering all aspects of custom layout with multiple hands on projects.
Course starts with detailed sessions on semiconductors, Ohms law, Kirchoff law's, Diode-operation, MOSFET's, MOSEFT operations, second order effects, FinFET's, and detailed fabrication process, which is followed by assignments and hands on projects.
Course will also include detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures. Followed by various analog layout techniques with detailed discussion on Mismatches & Matching, Noises & Coupling, various failure mechanisms which includes Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD.
Analog layout techniques will involve multiple hands on projects covering various concepts such as common centroid, inter digitation, resistor matching, capacitor matching and opamp circuits, current mirrors, PLL's, ADC's, DAC's, Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines, Large drivers, LNA & Mixers, and Sense amplifier & Bit cell development.
PCIe Transaction Layer VIP Development Training
ARM Architecture Training
VLSI Front End Training for Freshers
VLSI Front end training for freshers making BTech & MTech freshers industry ready. Course covers following aspects.
1. VLSI & SOC Design Flow
2. UNIX & Revision Management
3. Verilog Training
4. Systemverilog fro Functional Verification
5. UVM Essentials
6. Advanced Digital Design
Physical Design Basics
This course covers essential basics of Physical Design. This course ensures that all students in a Physical Design training batch are at same understanding level.
- Introduction to CMOS circuits
- MOS transistor theory, processing technology
- Combinational circuits & Logic Design
- Logical Effort & Power
- Testing & Verification
- Wires and Scaling
- Macros
UVM for Functional Verification
UVM & OVM for Functional Verification (VT-VM) course is structured to enable engineers develop their skills in full breadth of UVM & OVM features in complex testbench development. VT-VM course is targeted for verification engineers who are used to SV based functional verification and would like to explore UVM & OVM based verification. Course has been framed in a way to make UVM & OVM learning a fun and interesting activity. Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple industry standard projects, all of these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VM.
System Verilog for functional verification
SystemVerilog for Functional Verification course is structured to enable engineers to develop their skills in full breadth of systemverilog features. VT-SV course covers all aspects of functional verification including constrained random verification, assertion based verification and coverage driven verification. VT-SV course has been framed to fit to every functional verification engineer requirements and also targeted for graduates aspiring to make career in VLSI Front End domain. Course approaches by teaching basic concepts to most advanced aspects of SV with relevant examples to enable easier understanding of concepts.
VT-SV course does not just focus on teaching SV constructs and their usage. Course also puts lot of emphasis on teaching industry standard AXI protocol and developing Verification IP for same. Course also includes 1 industry standard project. All these projects are executed from scratch with students working on complete flow starting from specification reading, feature listing down, testbench architecture creation, component coding and testcase development till verification closure using coverage and regression as verification closure criteria.
Quality VLSI Training at Affordable Fee.
